Realtek RTL8169 Manual page 8

GNTB I
ACK64B S/T/S
REQB T/S
REQ64B S/T/S
IDSEL I
INTAB O/D
IRDYB S/T/S
TRDYB S/T/S
PAR T/S
PAR64 T/S
cont...
2002/03/27
177
Grant: This signal is asserted low to indicate to the RTL8169 that the
central arbiter has granted the ownership of the bus to the RTL8169.
This input is used when the RTL8169 is acting as a bus master.
31 Acknowledge 64-bit Transfer: This signal is asserted low by the
device that has positively decoded its address as the target of the current
access, indicates the target is willing to transfer data using 64 bits.
ACK64B has the same timing as DEVSELB.
178
Request: The RTL8169 will assert this signal low to request the
ownership of the bus from the central arbiter.
32 Request 64-bit Transfer: The RTL8169 asserts this signal low to
indicate that it wants to perform a 64-bit data transfer.
If the RTL8169 sees the REQ64B asserted on the rising edge of PCI
RSTB, the RTL8169 is on 64-bit slot and is capable of 64-bit
transaction. Otherwise, the RTL8169 is on 32-bit slot.
191 Initialization Device Select: This pin allows the RTL8169 to identify
when configuration read/write transactions are intended for it.
174 Interrupt A: Used to request an interrupt. It is asserted low when an
interrupt condition occurs, as defined by the Interrupt Status, Interrupt
Mask.
204 Initiator Ready: This indicates the initiating agent's ability to complete
the current data phase of the transaction.
As a bus master, this signal will be asserted low when the RTL8169 is
ready to complete the current data phase transaction. This signal is used
in conjunction with the TRDYB signal. Data transaction takes place at
the rising edge of CLK when both IRDYB and TRDYB are asserted
low. As a target, this signal indicates that the master has put data on the
bus.
205
Target Ready: This indicates the target agent's ability to complete the
current phase of the transaction.
As a bus master, this signal indicates that the target is ready for the data
during write operations and with the data during read operations. As a
target, this signal will be asserted low when the (slave) device is ready
to complete the current data phase transaction. This signal is used in
conjunction with the IRDYB signal. Data transaction takes place at the
rising edge of CLK when both IRDYB and TRDYB are asserted low.
5 Parity: This signal indicates even parity across AD31-0 and C/BE3-0
including the PAR pin. PAR is stable and valid one clock after each
address phase. For data phase, PAR is stable and valid one clock after
either IRDYB is asserted on a write transaction or TRDYB is asserted
on a read transaction. Once PAR is valid, it remains valid until one clock
after the completion of the current data phase. As a bus master, PAR is
asserted during address and write data phases. As a target, PAR is
asserted during read data phases.
39 Parity Upper Double Word: This signal indicates even parity across
AD63-32 and C/BE7-4 including the PAR64 pin. PAR64 is valid one
clock after each address phase on any transaction in which REQ64B is
asserted. PAR64 is stable and valid for 64-bit data phase one clock after
either IRDYB is asserted on a write transaction or TRDYB is asserted
on a read transaction. As a bus master, PAR64 is asserted during address
and write data phases. As a target, the RTL8169 only supports 32-bit
transfers, so it will not assert PAR64.
8
RTL8169
Rev.1.21