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REALTEK SINGLE CHIP
FAST ETHERNET CONTROLLER
WITH POWER MANAGEMENT
1. Features........................................................................ 2
2. General Description .................................................... 3
3. Pin Assignments .......................................................... 4
4. Pin Description ............................................................ 6
4.1 Power Management/Isolation Interface.................. 6
4.2 PCI Interface .......................................................... 6
4.3 EPROM/EEPROM Interface.................................. 8
4.4 Power Pins.............................................................. 8
4.5 LED Interface ......................................................... 8
4.6 Attachment Unit Interface ...................................... 9
4.7 Test and Other Pins ................................................ 9
5. Register Descriptions ................................................ 10
5.2 Transmit Status Register....................................... 13
5.3 ERSR: Early Rx Status Register........................... 14
5.4 Command Register ............................................... 14
5.5 Interrupt Mask Register........................................ 15
5.6 Interrupt Status Register....................................... 15
5.7 Transmit Configuration Register.......................... 16
5.8 Receive Configuration Register ........................... 17
5.9 9346CR: 93C46 Command Register .................... 19
5.10 CONFIG 0: Configuration Register 0 ................ 20
5.11 CONFIG 1: Configuration Register 1 ................ 20
5.12 Media Status Register......................................... 21
5.13 CONFIG 3: Configuration Register3 ................. 22
5.14 CONFIG 4: Configuration Register4 ................. 23
5.15 Multiple Interrupt Select Register ...................... 24
5.16 PCI Revision ID ................................................. 24
5.18 Basic Mode Control Register ............................. 25
5.19 Basic Mode Status Register................................ 26
5.20 Auto-Negotiation Advertisement Register ......... 27
5.22 Auto-Negotiation Expansion Register................ 28
5.23 Disconnect Counter ............................................ 29
5.24 False Carrier Sense Counter ............................... 29
5.25 NWay Test Register ........................................... 29
5.26 RX_ER Counter ................................................. 29
5.27 CS Configuration Register ................................. 30
5.28 Config5: Configuration Register 5 ..................... 31
2001-11-9
Tel: +49(0)234-9351135 · Fax: +49(0)234-9351137 E -MAIL:
RTL8100B(L)
1
info@cornelius-consult.de
6. EEPROM (93C46) Contents .....................................32
7. PCI Configuration Space Registers..........................35
7.1 PCI Configuration Space Table ............................35
7.2 PCI Configuration Space Functions......................37
7.4 PCI Power Management Functions.......................41
7.5 VPD (Vital Product Data) .....................................43
8. Block Diagram ...........................................................44
9. Functional Description ..............................................45
9.1 Transmit operation ................................................45
9.2 Receive operation..................................................45
9.3 Wander Compensation..........................................45
9.4 Signal Detect.........................................................45
9.5 Line Quality Monitor ............................................45
9.6 Clock Recovery Module .......................................45
9.7 Loopback Operation..............................................45
9.8 Tx Encapsulation ..................................................46
9.9 Collision................................................................46
9.10 Rx Decapsulation ................................................46
9.11 Flow Control .......................................................46
9.11.1. Control Frame Transmission .......................46
9.11.2. Control Frame Reception ............................46
9.12 LED Functions ....................................................47
9.12.1 10/100 Mbps Link Monitor ..........................47
9.12.2 LED_RX ......................................................47
9.12.3 LED_TX.......................................................47
9.12.4 LED_TX+LED_RX .....................................48
10. Application Diagram ...............................................48
11. Electrical Characteristics ........................................49
11.1 Temperature Limit Ratings .................................49
11.2 DC Characteristics ..............................................49
11.2.1 Supply voltage..............................................49
11.2.2 Supply voltage..............................................49
11.3 AC Characteristics ..............................................50
11.3.1 PCI Bus Operation Timing...........................50
12. Mechanical Dimensions ...........................................56
12.1 QFP .....................................................................56
12.2 LQFP...................................................................57
http://www.cornelius-consult.de
RTL8100B(L)
Rev.1.41
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Table of Contents
Related Manuals for Realtek RTL8100B
Summary of Contents for Realtek RTL8100B
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Page 1: Table Of Contents
RTL8100B(L) 1. Features................ 2 6. EEPROM (93C46) Contents ........32 2. General Description ............ 3 6.1 Summary of the RTL8100B(L) EEPROM Registers...34 6.2 Summary of EEPROM Power Management Registers .34 3. Pin Assignments ............4 4. Pin Description ............6 7. PCI Configuration Space Registers......35 4.1 Power Management/Isolation Interface.... -
Page 2: Features
* Third-party brands and names are the property of their Supports auxiliary power-on internal reset, to be ready respective owners. Note: The model number of the QFP package is RTL8100B. The LQFP package model number is RTL8100BL. 2001-11-9 Rev.1.41 Tel: +49(0)234-9351135 · Fax: +49(0)234-9351137 E -MAIL: info@cornelius-consult.de... -
Page 3: General Description
To provide cost down support, the RTL8100B(L) is capable of using a 25MHz crystal or OSC as its internal clock source. The RTL8100B(L) keeps network maintenance costs low and eliminates usage barriers. It is the easiest way to upgrade a network from 10 to 100Mbps. -
Page 4: Pin Assignments
47 EEDI 84 GNTB 46 EEDO 85 REQB 86 AD31 45 AD0 87 AD30 44 AD1 88 GND 43 GND RTL8100B QFP 42 AD2 89 AD29 41 AD3 90 VDD 40 NC 91 AD28 92 AD27 39 VDD 93 AD26... - Page 5 RTL8100B(L) 63 RTT3 64 LWAKE 62 GND 65 RTSET 61 X1 66 GND 60 X2 67 RXIN- 59 AVDD 68 RXIN+ 58 AVDD25 69 NC 57 PMEB 70 AVDD 56 GND 71 TXD- 55 VCTRL 72 TXD+ 54 NC 73 GND...
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Page 6: Pin Description
RTL8100B(L) to request a change in its current power management state and/or to indicate that a power management event has occurred. ISOLATEB Isolate Pin: Active low. Used to isolate the RTL8100B(L) from the PCI (ISOLATE#) bus. The RTL8100B(L) does not drive its PCI outputs (excluding PME#) and does not sample its PCI input (including RST# and PCICLK) as long as the Isolate pin is asserted. - Page 7 Grant: This signal is asserted low to indicate to the RTL8100B(L) that the central arbiter has granted ownership of the bus to the RTL8100B (L). This input is used when the RTL8100B(L) is acting as a bus master. REQB Request: The RTL8100B(L) will assert this signal low to request the ownership of the bus from the central arbiter.
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Page 8: Eprom/Eeprom Interface
Pin No Description Aux. Power Detect: This pin is used to notify the RTL8100B(L) of the existence of Aux. power during initial power-on or a PCI reset. This pin should be pulled high to the Aux. power via a resistor to detect the Aux. -
Page 9: Attachment Unit Interface
This pin must be pulled low by a resistor. Please refer to the application circuit for the correct value. VCTRL Analog Use this pin and an external PNP type transistor to generate +2.5V for the RTL8100B(L). 7,35,40, 52,53, Reserved 54, 69, 76, 78 2001-11-9 Rev.1.41... -
Page 10: Register Descriptions
RTL8100B(L) 5. Register Descriptions The RTL8100B(L) provides the following set of operational registers mapped into PCI memory space or I/O space. Offset Description 0000h IDR0 ID Register 0: ID registers 0-5 are only permitted to read/write by 4-byte access. Read access can be byte, word, or double word access. - Page 11 RTL8100B(L) 0052h CONFIG1 Configuration Register 1 0053H Reserved R /W 0054h-0057h TimerInt Timer Interrupt Register: Once having written a nonzero value to this register, the Timeout bit of the ISR register will be set whenever the TCTR reaches to this value. The Timeout bit will never be set as long as the TimerInt register is zero.
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Page 12: Receive Status Register In Rx Packet Header
RTL8100B(L) 00D2h LSBCRC6 LSB of the mask byte of wakeup frame6 within offset 12 to 75 00D3h LSBCRC7 LSB of the mask byte of wakeup frame7 within offset 12 to 75 00D4h-00D7h Reserved 00D8h Config5 Configuration register 5 00D9h-00FFh Reserved 5.1 Receive Status Register in Rx packet header... -
Page 13: Transmit Status Register
(TSD0-3)(Offset 0010h-001Fh, R/W) The read-only bits (CRS, TABT, OWC, CDH, NCC3-0, TOK, TUN) will be cleared by the RTL8100B(L) when the Transmit Byte Count (bits 12-0) in the corresponding Tx descriptor is written. It is not affected when software writes to these bits. These registers are only permitted to write by double-word access. -
Page 14: Ersr: Early Rx Status Register
(Offset 0037h, R/W) This register is used for issuing commands to the RTL8100B(L). These commands are issued by setting the corresponding bits for the function. A global software reset along with individual reset and enable/disable for transmitter and receiver are provided here. -
Page 15: Interrupt Mask Register
IMR. Reading the ISR clears all interrupts. Writing to the ISR has no effect. Symbol Description SERR System Error: Set to 1 when the RTL8100B(L) signals a system error on the PCI bus. TimeOut Time Out: Set to 1 when the TCTR register reaches to the value of the TimerInt register. -
Page 16: Transmit Configuration Register
RTL8100B(L) 5.7 Transmit Configuration Register (Offset 0040h-0043h, R/W) This register defines the Transmit Configuration for the RTL8100B(L). It controls such functions as Loopback, programmable Interframe Gap, Fill and Drain Thresholds, and maximum DMA burst size. Symbol Description Reserved 30-26 HWVERID_A... -
Page 17: Receive Configuration Register
5.8 Receive Configuration Register (Offset 0044h-0047h, R/W) This register is used to set the receive configuration for the RTL8100B(L). Receive properties such as accepting error packets, runt packets, setting the receive drain threshold etc. are controlled here. Symbol... - Page 18 111 = Unlimited WRAP When set to 0: The RTL8100B(L) will transfer the rest of the packet data into the beginning of the Rx buffer if this packet has not been completely moved into the Rx buffer and the transfer has arrived at the end of the Rx buffer.
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Page 19: 9346Cr: 93C46 Command Register
(Offset 0050h, R/W) This register is used for issuing commands to the RTL8100B(L). These commands are issued by setting the corresponding bits for the function. A warm software reset along with individual reset and enable/disable for transmitter and receiver are provided as well. -
Page 20: Config 0: Configuration Register 0
Writing 1 is 1. Writing 0 is 0. When the command register bits IOEN, MEMEN, and BMEN of the PCI configuration space are written, the RTL8100B(L) will clear this bit automatically. LWACT LWAKE active mode: The LWACT bit and LWPTN bit in CONFIG4 register are used to program the LWAKE pin’s output signal. -
Page 21: Media Status Register
TXPF Set, when RTL8100B(L) sends pause packet. Reset, when RTL8100B(L) sends timer done packet. RXPF Pause Flag: Set, when RTL8100B(L) is in backoff state because a pause packet received. Reset, when pause state is clear. 2001-11-9 Rev.1.41 Tel: +49(0)234-9351135 · Fax: +49(0)234-9351137 E -MAIL: info@cornelius-consult.de... -
Page 22: Config 3: Configuration Register3
Magic Magic Packet: This bit is valid when the PWEn bit of the CONFIG1 register is set. The RTL8100B(L) will assert the PMEB signal to wakeup the operating system when the Magic Packet is received. Once the RTL8100B(L) has been enabled for Magic Packet wakeup... -
Page 23: Config 4: Configuration Register4
Long Wake-up Frame: The initial value comes from EEPROM autoload. Set to 0: The RTL8100B(L) supports up to 8 wake-up frames, each with masked bytes selected from offset 12 to 75. Set to 1: The RTL8100B(L) supports up to 5 wake-up frames, each... -
Page 24: Multiple Interrupt Select Register
(Offset 005Ch-005Dh, R/W) If the received packet data is not a familiar protocol (IPX, IP, NDIS, etc.) to the RTL8100B(L), RCR<ERTH[3:0]> will not be used to transfer data in early mode. This register will be written to the received data length in order to make an early Rx interrupt for the unfamiliar protocol. -
Page 25: Transmit Status Of All Descriptors (Tsad) Register
RTL8100B(L) 5.17 Transmit Status of All Descriptors (TSAD) Register (Offset 0060h-0061h, R/W) Symbol Description TOK3 TOK bit of Descriptor 3 TOK2 TOK bit of Descriptor 2 TOK1 TOK bit of Descriptor 1 TOK0 TOK bit of Descriptor 0 TUN3 TUN bit of Descriptor 3... -
Page 26: Basic Mode Status Register
RTL8100B(L) 5.19 Basic Mode Status Register (Offset 0064h-0065h, R) Name Description/Usage Default/Attribute 100Base-T4 1 = enable 100Base-T4 support; 0 = suppress 100Base-T4 support. 0, RO 100Base_TX_ FD 1 = enable 100Base-TX full duplex support; 0 = suppress 1, RO 100Base-TX full duplex support. -
Page 27: Auto-Negotiation Advertisement Register
RTL8100B(L) 5.20 Auto-Negotiation Advertisement Register (Offset 0066h-0067h, R/W) This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto-negotiation. Name Description/Usage Default/Attribute Next Page bit. 0, RO 1 = transmitting the protocol specific data page;... -
Page 28: Auto-Negotiation Link Partner Ability Register
RTL8100B(L) 5.21 Auto-Negotiation Link Partner Ability Register (Offset 0068h-0069h, R) This register contains the advertised abilities of the Link Partner as received during Auto-negotiation. The content changes after the successful Auto-negotiation if Next-pages are supported. Name Description/Usage Default/Attribute Next Page bit. -
Page 29: Disconnect Counter
RTL8100B(L) 5.23 Disconnect Counter (Offset 006Ch-006Dh, R) Name Description/Usage Default/Attribute 15-0 DCNT This 16-bit counter increments by 1 for every disconnect event. It h'[0000], rolls over when becomes full. It is cleared to zero by read command. 5.24 False Carrier Sense Counter (Offset 006Eh-006Fh, R) This counter provides information required to implement the “FalseCarriers”... -
Page 30: Cs Configuration Register
RTL8100B(L) 5.27 CS Configuration Register (Offset 0074h-0075h, R/W) Name Description/Usage Default/Attribute Testfun 1 = Auto-neg speeds up internal timer 0,WO 14-10 Reserved Active low TPI link disable signal. When low, TPI still transmits 1, RW link pulses and TPI stays in good link state. -
Page 31: Config5: Configuration Register 5
0: The PME_Status bit can only be reset by software. Config5 register, offset D8h: (SYM_ERR register is changed to Config5, the function of SYM_ERR register is no longer supported by RTL8100B(L).) The 3 bits (bit2-0) are auto-loaded from EEPROM Config5 byte to RTL8100B(L) Config5 register. 2001-11-9 Rev.1.41 Tel: +49(0)234-9351135 ·... -
Page 32: Eeprom (93C46) Contents
The 93C46 is a 1K-bit EEPROM. Although it is actually addressed by words, its contents are listed below by bytes for convenience. The RTL8100B(L) performs a series of EEPROM read operations from the 93C46 addresses 00H to 31H. It is suggested to obtain Realtek approval before changing the default settings of the EEPROM. - Page 33 PHY Parameter 1-T for RTL8100B(L). Operational registers of the RTL8100B(L) are from 78h to 7Bh. PHY2_PARM_T Reserved. Do not change this field without Realtek approval. PHY Parameter 2-T for RTL8100B(L). Operational register of the RTL8100B(L) is 80h. 2Dh-31h Reserved. 32h-33h CheckSum Reserved.
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Page 34: Summary Of The Rtl8100B(L) Eeprom Registers
RTL8100B(L) 6.1 Summary of the RTL8100B(L) EEPROM Registers Offset Name Type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00h-05h IDR0 – IDR5 R/W CONFIG0 DVRLOAD MEMMAP CONFIG1 LEDS1 LEDS0 LWACT IOMAP PMEN LEDS1 LEDS0 DVRLOAD LWACT PMEN TxFCE RxFCE... -
Page 35: Pci Configuration Space Registers
RTL8100B(L) 7. PCI Configuration Space Registers 7.1 PCI Configuration Space Table Name Type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Command PERRSP BMEN MEMEN IOEN PERRSP BMEN MEMEN IOEN FBTBEN SERREN SERREN Status FBBC NewCap DPERR SSERR RMABT RTABT... - Page 36 RTL8100B(L) PME_D3 PME_D3 PME_D2 PME_D1 PME_D0 Aux_I_b2 cold PMCSR Power State Power State PME_Status PME_En PME_Status PME_En 56h–5Fh RESERVED VPDID NextPtr Flag VPD R/W VPDADDR VPDADDR VPDADD VPDADD VPDADD VPDADD VPDADD VPDADD Address Flag VPDADDR VPDADD VPDADD VPDADD VPDADD VPDADD...
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Page 37: Pci Configuration Space Functions
BMEN Bus Master Enable: When set to 1, the RTL8100B(L) is capable of acting as a bus master. When set to 0, it is prohibited from acting as a PCI bus master. For the normal operation, this bit must be set by the system BIOS. - Page 38 Because the PCI version 2.1 specification does not define any specific value for network devices, PIFR = 00h. SCR: Sub-Class Register The Sub-class register is an 8-bit register that identifies the function of the RTL8100B(L). SCR = 00h indicates that the RTL8100B(L) is an Ethernet controller.
- Page 39 MNGNT: Minimum Grant Timer: Read only Specifies how long a burst period the RTL8100B(L) needs at 33 MHz clock rate in units of 1/4 microsecond. This field will be set to a value from the external EEPROM. If there is no EEPROM, this field will default to a value of 20h.
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Page 40: Default Values After Power-On (Rstb Asserted)
RTL8100B(L) 7.3 Default Values after Power-on (RSTB asserted) PCI Configuration Space Table Name Type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Command PERRSP BMEN MEMEN IOEN SERREN Status NewCap DPERR SSERR RMABT RTABT STABT Revision ID PIFR LTR7 LTR6... -
Page 41: Pci Power Management Functions
Link Wakeup occurs only when the following conditions are met: ♦ The LinkUp bit (CONFIG3#4) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the RTL8100B(L) is in isolation state, or the PME# can be asserted in current power state. - Page 42 RTL8100B(L) ♦ The Magic bit (CONFIG3#5) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the RTL8100B(L) is in isolation state, or the PME# can be asserted in current power state. ♦ The Magic Packet pattern matches, i.e. 6 * FFh + MISC(can be none)+ 16 * DID(Destination ID) in any part of a valid (Fast) Ethernet packet.
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Page 43: Vpd (Vital Product Data)
1. Write VPD register: (write data to 93C46) Write the flag bit to a one at the same time the VPD address is written. When the flag bit is set to zero by the RTL8100B(L), the VPD data (all 4 bytes) has been transferred from the VPD data register to the 93C46. -
Page 44: Block Diagram
RTL8100B(L) 8. Block Diagram EEPROM LED Driver Interface Power Control Logic Early Interrupt Threshold Register Interrupt Control Early Interrupt Logic Control Logic Interface Transmit/ FIFO Receive FIFO Control Logic Logic Interface Interface 100M Data Descrambler RXC 25M Decoder Alignment 10/100... -
Page 45: Functional Description
The host CPU initiates a transmit by storing an entire packet of data in one of the descriptors in the main memory. When the entire packet has been transferred to the Tx buffer, the RTL8100B(L) is instructed to move the data from the Tx buffer to the internal transmit FIFO in PCI bus master mode. -
Page 46: Tx Encapsulation
After detecting receive activity on the line, the RTL8100B(L) starts to process the preamble bytes based on the mode of operation. While operating in 100Base-Tx mode, the RTL8100B(L) expects the frame to start with the symbol pair JK in the first bye of the 8-byte preamble. -
Page 47: Led Functions
RTL8100B(L) 9.12 LED Functions 9.12.1 10/100 Mbps Link Monitor The Link Monitor senses the link integrity or if a station is down. 9.12.2 LED_RX In 10/100 Mbps mode, the LED function is like the RTL8139C(L). Power On LED = Low... -
Page 48: Led_Tx+Led_Rx
RTL8100B(L) 9.12.4 LED_TX+LED_RX Power On LED = Low Tx or Rx Packet? LED = High for (100 +- 10) ms LED = Low for (12 +- 2) ms 10. Application Diagram EEPROM RTL8100B(L) RJ45 Magetics Auxiliary Power PCI INTERFACE 2001-11-9 Rev.1.41... -
Page 49: Electrical Characteristics
RTL8100B(L) 11. Electrical Characteristics 11.1 Temperature Limit Ratings Parameter Minimum Maximum Units °C Storage temperature +125 °C Operating temperature 11.2 DC Characteristics 11.2.1 Supply voltage Vcc = 3.0V min. to 3.6V max. Symbol Parameter Conditions Minimum Maximum Units V OH... -
Page 50: Ac Characteristics
RTL8100B(L) 11.3 AC Characteristics 11.3.1 PCI Bus Operation Timing Target Read Target Write 2001-11-9 Rev.1.41 Tel: +49(0)234-9351135 · Fax: +49(0)234-9351137 E -MAIL: info@cornelius-consult.de http://www.cornelius-consult.de... - Page 51 RTL8100B(L) Configuration Read Configuration Write 2001-11-9 Rev.1.41 Tel: +49(0)234-9351135 · Fax: +49(0)234-9351137 E -MAIL: info@cornelius-consult.de http://www.cornelius-consult.de...
- Page 52 RTL8100B(L) BUS Arbitration Memory Read 2001-11-9 Rev.1.41 Tel: +49(0)234-9351135 · Fax: +49(0)234-9351137 E -MAIL: info@cornelius-consult.de http://www.cornelius-consult.de...
- Page 53 RTL8100B(L) Memory Write Target Initiated Termination - Retry 2001-11-9 Rev.1.41 Tel: +49(0)234-9351135 · Fax: +49(0)234-9351137 E -MAIL: info@cornelius-consult.de http://www.cornelius-consult.de...
- Page 54 RTL8100B(L) Target Initiated Termination - Disconnect Target Initiated Termination - Abort 2001-11-9 Rev.1.41 Tel: +49(0)234-9351135 · Fax: +49(0)234-9351137 E -MAIL: info@cornelius-consult.de http://www.cornelius-consult.de...
- Page 55 RTL8100B(L) Master Initiated Termination – Abort Parity Operation - one example 2001-11-9 Rev.1.41 Tel: +49(0)234-9351135 · Fax: +49(0)234-9351137 E -MAIL: info@cornelius-consult.de http://www.cornelius-consult.de...
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Page 56: Mechanical Dimensions
47.2 55.1 1.00 1.20 1.40 SCALE 88.6 94.5 104.3 2.25 2.40 2.65 CHECK Ricardo Chen DATE 0.10 SHT NO. 1 OF 0° 12° 0° 12° θ REALTEK SEMICONDUCTOR CORP. 2001-11-9 Rev.1.41 Tel: +49(0)234-9351135 · Fax: +49(0)234-9351137 E -MAIL: info@cornelius-consult.de http://www.cornelius-consult.de... -
Page 57: Lqfp
VERSION 1 0° 3.5° 9° 0° 3.5° 9° PAGE θ θ 0° 0° CHECK DWG NO. LQ100 - P1 θ 12°TYP 12°TYP DATE 12°TYP 12°TYP θ REALTEK SEMICONDUCTOR CORP. 2001-11-9 Rev.1.41 Tel: +49(0)234-9351135 · Fax: +49(0)234-9351137 E -MAIL: info@cornelius-consult.de http://www.cornelius-consult.de... - Page 58 RTL8100B(L) Realtek Semiconductor Corp. Headquarters No. 2, Industry East Road IX, Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Tel : 886-3-5780211 Fax : 886-3-5776047 WWW: www.realtek.com.tw 2001-11-9 Rev.1.41 Tel: +49(0)234-9351135 · Fax: +49(0)234-9351137 E -MAIL: info@cornelius-consult.de http://www.cornelius-consult.de...
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