Realtek RTL8169 Manual page 44

SCR: Sub-Class Register
The Sub-class register is an 8-bit register that identifies the function of the RTL8169. SCR = 00h indicates that the
RTL8169 is an Ethernet controller.
BCR: Base-Class Register
The Base-class register is an 8-bit register that broadly classifies the function of the RTL8169. BCR = 02h indicates that
the RTL8169 is a network controller.
CLS: Cache Line Size
Specifies, in units of 32-bit words (double-words), the system cache line size. The RTL8169 supports cache line size of
8, and 16 longwords (DWORDs). The RTL8169 uses Cache Line Size for PCI commands that are cache oriented, such as
memory-read-line, memory-read-multiple, and memory-write-and-invalidate.
LTR: Latency Timer Register
Specifies, in units of PCI bus clocks, the value of the latency timer of the RTL8169.
When the RTL8169 asserts FRAMEB, it enables its latency timer to count. If the RTL8169 deasserts FRAMEB prior to
count expiration, the content of the latency timer is ignored. Otherwise, after the count expires, the RTL8169 initiates
transaction termination as soon as its GNTB is deasserted. Software is able to read or write, and the default value is 00h.
HTR: Header Type Register
Reads will return a 0, writes are ignored.
BIST: Built-in Self Test
Reads will return a 0, writes are ignored.
IOAR: This register specifies the BASE IO address which is required to build an address map during configuration. It also
specifies the number of bytes required as well as an indication that it can be mapped into IO space. Britain
Bit Symbol
31:8 IOAR31-8 BASE IO Address: This is set by software to the Base IO address for the operational register map.
7:2 IOSIZE Size Indication: Read back as 0. This allows the PCI bridge to determine that the RTL8169 requires
256 bytes of IO space.
1 - Reserved
0 IOIN IO Space Indicator: Read only. Set to 1 by the RTL8169 to indicate that it is capable of being mapped
into IO space.
MEMAR: This register specifies the base memory address for memory accesses to the RTL8169 operational registers. This
register must be initialized prior to accessing any RTL8169's register with memory access.
Bit Symbol
31:8 MEM31-8 Base Memory Address: This is set by software to the base address for the operational register map.
7:4 MEMSIZE Memory Size: These bits return 0, which indicates that the RTL8169 requires 256 bytes of Memory Space.
3 MEMPF Memory Prefetchable: Read only. Set to 0 by the RTL8169.
2:1 MEMLOC Memory Location Select: Read only. Set to 0 by the RTL8169. This indicates that the base register is
32-bits wide and can be placed anywhere in the 32-bit memory space.
0 MEMIN Memory Space Indicator: Read only. Set to 0 by the RTL8169 to indicate that it is capable of being
mapped into memory space.
CISPtr: CardBus CIS Pointer. This field is valid only when CardB_En (bit3, Config3) = 1. The value of this register is
auto-loaded from 93C46 or 93C56 (from offset 30h-31h).
- Bit 2-0: Address Space Indicator
Bit2:0
7
6:1
0
- Bit27-3: Address Space Offset
- Bit31-28: ROM Image number
2002/03/27
The CIS begins in the Expansion ROM space.
The CIS begins in the memory address governed by one of the six Base
Address Registers. Ex., if the value is 2, then the CIS begins in the memory
address space governed by Base Address Register 2.
Not supported. (CIS begins in device-dependent configuration space.)
Description
Description
Meaning
44
RTL8169
Rev.1.21