Register Descriptions - Realtek RTL8169 Manual

6. Register Descriptions

The RTL8169 provides the following set of operational registers mapped into PCI memory space or I/O space.
Offset R/W
0000h R/W
0001h R/W
0002h R/W
0003h R/W
0004h R/W
0005h R/W
0006h-0007h
0008h R/W
0009h R/W
000Ah R/W
000Bh R/W
000Ch R/W
000Dh R/W
000Eh R/W
000Fh R/W
0010h-0017h R/W
0018h-001Fh
0020h-0027h R/W
0028h-002Fh R/W
0030h-0033h R/W
0034h-0035h R
0036h R
0037h R/W
0038h W
0039h-003Bh
003Ch-003Dh R/W
003Eh-003Fh R/W
0040h-0043h R/W
0044h-0047h R/W
0048h-004Bh R/W
004Ch-004Fh R/W
0050h R/W
0051h R/W
0052h R/W
0053h R/W
0054h R/W
cont...
2002/03/27
Tag
IDR0
IDR1
IDR2
IDR3
IDR4
IDR5
- -
MAR0
MAR1
MAR2
MAR3
MAR4
MAR5
MAR6
MAR7
DTCCR
- -
TNPDS
THPDS
FLASH
ERBCR
ERSR
CR
TPPoll
- -
IMR
ISR
TCR
RCR
TCTR
MPC
9346CR
CONFIG0
CONFIG1
CONFIG2
CONFIG3
ID Register 0: The ID registers 0-5 are only permitted to write by
4-byte access. Read access can be byte, word, or double word access.
The initial value is autoloaded from EEPROM EthernetID field.
ID Register 1
ID Register 2
ID Register 3
ID Register 4
ID Register 5
Reserved
Multicast Register 0: The MAR registers 0-7 are only permitted to
write by 4-bye access. Read access can be byte, word, or double word
access. Driver is responsible for initializing these registers.
Multicast Register 1
Multicast Register 2
Multicast Register 3
Multicast Register 4
Multicast Register 5
Multicast Register 6
Multicast Register 7
Dump Tally Counter Command Register (64-byte alignment)
Reserved
Transmit Normal Priority Descriptors: Start address (64-bit).
(256-byte alignment)
Transmit High Priority Descriptors: Start address (64-bit).
(256-byte alignment)
Flash memory read/write register
Early Receive (Rx) Byte Count Register
Early Rx Status Register
Command Register
Transmit Priority Polling register
Reserved
Interrupt Mask Register
Interrupt Status Register
Transmit (Tx) Configuration Register
Receive (Rx) Configuration Register
Timer CounT Register:
general-purpose timer. Writing any value to this 32-bit register will
reset the original timer and begin the count from zero.
Missed Packet Counter: This 24-bit counter indicates the number of
packets discarded due to Rx FIFO overflow. After a s/w reset, MPC is
cleared. Only the lower 3 bytes are valid.
When any value is written to MPC, it will be reset.
93C46 (93C56) Command Register
Configuration Register 0
Configuration Register 1
Configuration Register 2
Configuration Register 3
13
Description
This register contains a 32-bit
RTL8169
Rev.1.21