Physical Layer Interfaces; Media Independent Interface (Mii); Gigabit Media Independent Interface (Gmii); Ten Bit Interface (Tbi) - Realtek RTL8169 Manual

9.7 Physical Layer Interfaces

The RTL8169 supports standard media independent MII and GMII for 10Mbps, 100Mbps, and 1000Mbps applications. The
RTL8169 also supports TBI (Ten-Bit Interface) for 1000Base-X applications by connecting to industry standard external
SERDES devices for fiber applications. The RTL8169 only operates in full-duplex mode in 1000Mbps for both GMII and TBI
applications. In addition, a management interface is defined for MII and GMII.

9.7.1 Media Independent Interface (MII)

The RTL81689 supports 10Mbps and 100Mbps physical layer devices through the MII as defined in the IEEE 802.3 (clause 22)
specifications. The MII consists of a transmit data interface (TxEN, TxER, TXD[3:0], and TxCLK), a receive data interface
(RxDV, RxER, RXD[3:0], and RxCLK), 2 status signals (CRS and COL) and a management interface (MDC and MDIO). In
this mode of operation, both Transmit and Receive clocks are supplied by the PHY.

9.7.2 Gigabit Media Independent Interface (GMII)

The RTL81689 can support 1000Mbps physical layer devices through the GMII as defined in the IEEE 802.3 (clause 35)
specifications. The GMII extends from the MII to use 8-bit data interfaces and to operate at a higher frequency. The GMII
consists of a transmit data interface (TxEN, TxER, TXD[7:0], and GTxCLK), a receive data interface (RxDV, RxER, RXD[7:0],
and RxCLK), 2 status signals (CRS and COL) and a management interface (MDC and MDIO). Many of the signals are shared
with the MII interface. One significant difference is the Transmit clock (GTxCLK) is supplied by the RTL81689 instead of the
PHY. The management interface (described later) is the same in both MII and GMII modes

9.7.3 Ten Bit Interface (TBI)

The TBI provides a port for transmit and receive data for interfacing to devices that support the 1000Base-X portion of the 802.3
specifications. This includes 1000Base-FX fiber devices. The port consists of data paths that are 10 bits wide in each direction as
well as control signals. This interface shares pins with the MII and GMII interfaces.

9.7.4 MII/GMII Management Interface

The MII/GMII management interface utilizes a communication protocol similar to a serial EEPROM. Signaling occurs on two
signals: clock (MDC) and data (MDIO). This protocol provides capability for addressing up to 32 individual Physical Media
Dependent (PMD) devices which share the same serial interface, and for addressing up to 32 16-bit read/write registers within
each PMD. The MII management protocol utilizes the following frame format: start bits (SB), opcode (OP), PMD address (PA),
register address (RA), line turnaround (LT) and data, as shown below.
i. Start bits are defined as <01>.
ii. Opcode bits are defined as <01> for a Write access and <10> for a Read access.
iii. PMD address is the device address.
iv. Register address is address of the register within that device.
v. Line turnaround bits will be <10> for Write accesses and will be <xx> for Read accesses. This allows time for the MII
lines to "turn around".
vi. Data is the 16 bits of data that will be written to or read from the PMD device.
A reset frame, defined as 32 consecutive 1s (FFFF FFFFh), is also provided. After power up, all MII PMD devices must wait for
a reset frame to be received prior to participating in MII management communication. Additionally, a reset frame may be issued
at any time to allow all connected PMDs to re-synchronize to the data traffic.
2002/03/27
SB OP PA
2 bits 2 bits 5 bits
MII Management Frame Format
RA LT
2
5 bits
bits
64
RTL8169
Data
16 bits
Rev.1.21