Pci Bus Operation Timing - Realtek RTL8169 Manual

11.3.3 PCI Bus Operation Timing

PCI Bus Timing Parameters
Symbol
T val CLK to Signal Valid Delay-bused signals
T val(ptp) CLK to Signal Valid Delay-point to point
T on Float to Active Delay
T off Active to Float Delay
Input Setup Time to CLK-bused signals
T su
Input Setup Time to CLK-point to point
T su(ptp)
T h Input Hold Time from CLK
T rst Reset active time after power stable
T rst-clk Reset active time after CLK STABLE
T rst-off Reset Active to Output Float delay
Trrsu REQB to REQ64B Setup Time
Trrh RSTB to REQ64B Hold Time
T rhfa RSTB High to First configuration Access
T rhff RSTB High to First FRAMEB assertion
CLK
INPUT
2002/03/27
Parameter
PCI Interface Timing Parameters
CLK
OUTPUT
DELAY
Tri-State
OUTPUT
Output Timing Measurement Condition
V_th
V_test
V_tl
Input Timing Measurement Conditions
Symbol
Vth
Vtf
Vtest
Vtrise
Vtfall
Vmax
Input Signal
Edge Rate
Measurement Condition Parameters
66MHz
Min Max
2 6
2 6
2
14
3
5
0
1
100
40
10*Tcyc
0 50
2^25
5
V_test
T_val
V_trise, V_tfall
V_test V_test
T_on
T_off
V_test
T_su T_h
inputs valid
Level
0.6Vcc
0.2Vcc
0.4Vcc
0.285Vcc
0.615Vcc
0.4Vcc
1
70
33MHz
Min Max Units
2 11
2 12
2
28
7
10
0
1
100
40
10*Tcyc
0 50
2^25 clocks
5 clocks
V_th
V_tl
V_th
V_tl
V_test V_max
Units
V
V
V
V
V
V
V/ns
RTL8169
ns
ns
ns
ns
ns
ns
ns
ms
us
ns
ns
ns
Rev.1.21