Memory Functions; Memory Read Line (Mrl); Memory Read Multiple (Mrm) - Realtek RTL8169 Manual

9.5 Memory Functions

9.5.1 Memory Read Line (MRL)

The Memory Read Line command reads more than a longword (DWORD) up to the cache line boundary in a prefetchable
address space. The Memory Read Line command is semantically identical to the Memory Read command except that it
additionally indicates that the master intends to fetch a complete cache line. This command is intended to be used with bulk
sequential data transfers where the memory system and the requesting master might gain some performance advantages by
reading up to a cache line boundary in response to the request rather than a single memory cycle. As with the Memory Read
command, pre-fetched buffers must be invalidated before any synchronization events are passed through this access path.
The RTL8169 performs MRL according to the following rules:
i. Read accesses that reach the cache line boundary use the Memory Read Line command (MRL) instead of the Memory
Read command.
ii. Read accesses that do not reach the cache line boundary use the Memory Read (MR) command.
iii. The Memory Read Line (MRL) command operates in conjunction with the Memory Read Multiple command (MRM).
iv. The RTL8169 will terminate the read transaction on the cache line boundary when it is out of resources on the transmit
DMA. For example, when the transmit FIFO is almost full.

9.5.2 Memory Read Multiple (MRM)

The Memory Read Multiple command is semantically identical to the Memory Read command except that it additionally
indicates that the master may intend to fetch more than one cache line before disconnecting. The memory controller should
continue pipelining memory requests as long as FRAMEB is asserted. This command is intended to be used with bulk sequential
data transfers where the memory system and the requesting master might gain some performance advantage by sequentially
reading ahead one or more additional cache line(s) when a software transparent buffer is available for temporary storage.
The RTL8169 performs MRM according to the following rules,
i. When the RTL8169 reads full cache lines, it will use the Memory Read Multiple command.
ii. If the memory buffer is not cache-aligned, the RTL8169 will use the Memory Read Line command to reach the cache line
boundary first.
Example:
Assume the packet length = 1514 byte, cache line size = 16 longwords (DWORDs), and Tx buffer start address =
64m+4 (m > 0).
;Step1: Memory Read Line (MRL)
;Data: (0-3) => (4-7) => (8-11) =>............ => (56-59)
;From Address: <64m+4>, <64m+8>, .........., <64m+60>
;Step2. Memory Read Multiple (MRM)
;Data: (60-63) => (64-67) => (68-71) => ................................. => (1454-1467)
;From Address: <64m+64>, <64m+68>, ......................., <64m+64+(16*4)*21+(16-1)*4>
;Step3. Memory Read(MR)
;Data: (1468-1471) => (1472-1475) => ................................., => (1510-1513)
;From Address:<64m+64+(16*4)*22>,<64m+64+(16*4)*22+4>,..,<64m+64+(16*4)*22+42>
Step1: Memory Read Multiple (MRM)
Data: (0-3) => (4-7) => (8-11) =>.............. => (1454-1467)
From Address: <64m+4>, <64m+8>, .........., <64m+64+(16*4)*21+(16-1)*4>
Step2. Memory Read(MRL)
Data: (1468-1471) => (1472-1475) => ................................., => (1510-1513)
From Address:<64m+64+(16*4)*22>,<64m+64+(16*4)*22+4>,..,<64m+64+(16*4)*22+42>
2002/03/27
(byte offset of the Tx packet)
(reach cache line boundary)
59
RTL8169
Rev.1.21