Memory Write And Invalidate (Mwi); Dual Address Cycle (Dac) - Realtek RTL8169 Manual

9.5.3 Memory Write and Invalidate (MWI)

The Memory Write and Invalidate command is semantically identical to the Memory Write command except that it additionally
guarantees a minimum transfer of one complete cache line; i.e., the master intends to write all bytes within the addressed cache
line in a single PCI transaction unless interrupted by the target. Note: All byte enables must be asserted during each data phase
for this command. The master may allow the transaction to cross a cache line boundary only if it intends to transfer the entire
next line also. This command requires implementation of a configuration register in the master indicating the cache line size and
may only be used with Linear Burst Ordering. It allows a memory performance optimization by invalidating a "dirty" line in a
write-back cache without requiring the actual write-back cycle, thus shortening access time. The RTL8169 uses the MWI
command while writing full cache lines, and the Memory Write command while writing partial cache lines.
The RTL8169 issues MWI command, instead of MW command on Rx DMA when the following requirements are met:
i. The Cache Line Size written in offset 0Ch of the PCI configuration space is 8 or 16 longwords (DWORDs).
ii. The accessed address is cache line aligned.
iii. The RTL8169 has at least 8/16 longwords (DWORDs) of data in its Rx FIFO.
iv. The MWI (bit 4) in the PCI Configuration Command register should be set to 1.
The RTL8169 uses the Memory Write (MW) command instead of the MWI whenever there any one of the above listed
requirements has failed. The RTL8169 terminates the WMI cycle at the end of the cache line when a WMI cycle has started and
at least one of the requirements are no longer held.
Example:
Assume Rx packet length = 1514 byte, cache line size = 16 DWORDs (longwords), and Rx buffer start address =
64m+4 (m > 0).
Step1: Memory Write (MW)
Data: (0-3) => (4-7) => (8-11) => ............ => (56-59)
To Address: <64m+4>, <64m+8>, ............., <64m+60>
Step2. Memory Write and Invalidate (MWI)
Data: (60-63) => (64-67) => (68-71) => ................................. => (1454-1457)
To Address: <64m+64>, <64m+68>, ........................., <64m+64+(16*4)*21+(16-1)*4>
Step3. Memory Write(MW)
Data: (1458-1461) => (1462-1465) => ................................... => (1512-1513)
To Address: <64m+64+(16*4)*22>, <64m+64+(16*4)*22+4>, , <64m+64+(16*4)*22+42>

9.5.4 Dual Address Cycle (DAC)

The Dual Address Cycle (DAC) command is used to transfer a 64-bit address to devices that support 64-bit addressing when the
address is not in the low 4 GB address space. The RTL8169 is capable of performing DAC, such that it is very competent as a
network server card in a heavy-duty server with the possibility of allocating a memory buffer above a 4GB memory address space.
2002/03/27
(byte offset of the Rx packet)
(reach cache line boundary)
60
RTL8169
Rev.1.21