Realtek RTL8169 Manual page 43

6 PERRSP
5 VGASNOOP VGA palette SNOOP: Read as 0, write operations have no effect.
4 MWIEN
3 SCYCEN
2 BMEN
1 MEMEN
0 IOEN
Status: The status register is a 16-bit register used to record status information for PCI bus related events. Reads to this register
behave normally. Writes are slightly different in that bits can be reset, but not set.
Bit Symbol
15 DPERR Detected Parity Error: This bit, when set, indicates that the RTL8169 has detected a parity error, even if
parity error handling is disabled in command register PERRSP bit.
14 SSERR Signaled System Error: This bit, when set, indicates that the RTL8169 has asserted the system error pin,
SERRB. Writing a 1 clears this bit to 0.
13 RMABT Received Master Abort: This bit, when set, indicates that the RTL8169 has terminated a master
transaction with master abort. Writing a 1 clears this bit to 0.
12 RTABT
Received Target Abort: This bit, when set, indicates that an RTL8169 master transaction was
terminated due to a target abort. Writing a 1 clears this bit to 0.
11 STABT Signaled Target Abort: This bit is set to 1 whenever the RTL8169 terminates a transaction with a target
abort. Writing a 1 clears this bit to 0.
10:9 DST1-0 Device Select Timing: These bits encode the timing of DEVSELB. They are set to 01b (medium),
indicating the RTL8169 will assert DEVSELB two clocks after FRAMEB is asserted.
8 DPD
Data Parity error Detected: This bit is set when the following conditions are met:
* The RTL8169 asserts parity error (PERRB pin) or it senses the assertion of PERRB pin by another device.
* The RTL8169 operates as a bus master for the operation that caused the error.
* The Command register PERRSP bit is set.
Writing a 1 clears this bit to 0.
7 FBBC
Fast Back-To-Back Capable: Config3<FbtBEn>=0, Read as 0, write operations have no effect.
Config3<FbtBEn>=1, Read as 1.
6 UDF User Definable Features Supported: Read as 0, and write operations have no effect. The RTL8169
does not support UDF.
5 66MHz 66MHz Capable: Read as 1, and write operations have no effect. The RTL8169 supports 66MHz PCI clock.
4 NewCap New Capability: Config3<PMEn>=0, Read as 0, and write operations have no effect.
Config3<PMEn>=1, Read as 1.
0:3 - Reserved
RID: Revision ID Register
The Revision ID register is an 8-bit register that specifies the RTL8169 controller revision number.
PIFR: Programming Interface Register
The programming interface register is an 8-bit register that identifies the programming interface of the RTL8169
controller. The PCI specification reversion 2.1 doesn't define any other specific value for network devices. So PIFR = 00h.
2002/03/27
Parity Error Response: When set to 1, the RTL8169 will assert the PERRB pin on the detection of a
data parity error when acting as the target, and will sample the PERRB pin as the master. When set to
0, any detected parity error is ignored and the RTL8169 continues normal operation.
Parity checking is disabled after hardware reset (RSTB).
Memory Write and Invalidate cycle Enable: This is an enable bit for using the Memory Write and
Invalidate command. When this bit is 1, the RTL8169 as a master may generate the command. When
this bit is 0, the RTL8169 may generate Memory Write command instead. State after PCI RSTB is 0.
Special Cycle Enable: Read as 0, write operations have no effect. The RTL8169 ignores all special
cycle operations.
Bus Master Enable: When set to 1, the RTL8169 is capable of acting as a PCI bus master. When set
to 0, it is prohibited from acting as a bus master.
For normal operations, this bit must be set by the system BIOS.
Memory Space Access: When set to 1, the RTL8169 responds to memory space accesses. When set to
0, the RTL8169 ignores memory space accesses.
I/O Space Access: When set to 1, the RTL8169 responds to IO space accesses. When set to 0, the
RTL8169 ignores I/O space accesses.
Description
43
RTL8169
Rev.1.21