Pci Interface - Realtek RTL8169 Manual

5.2 PCI Interface

Symbol Type
AD63-0 T/S
C/BE7-0B T/S
CLK I
CLKRUNB I/O
DEVSELB S/T/S
FRAMEB S/T/S
cont...
2002/03/27
Pin No
40, 42-44, 46, 50,
52-54, 56-59, 61-64,
66-67, 69-70, 73-76,
78-81, 83-85, 180-183,
185-188, 192-194,
196-199, 201, 9-12,
14-17, 20-22, 24-26,
28-29
34-35, 37-38, 190, 202,
7, 19
176
86
207
203
AD31-0: Low 32-bit PCI address and data multiplexed pins. The
address phase is the first clock cycle in which FRAMEB is asserted. During
the address phase, AD31-0 contains a physical address (32 bits). For I/O,
this is a byte address, and for configuration and memory, it is a double-word
address. The RTL8169 supports both big-endian and little-endian byte
ordering. Write data is stable and valid when IRDYB is asserted. Read data
is stable and valid when TRDYB is asserted. Data I is transferred during
those clocks where both IRDYB and TRDYB are asserted.
AD63-32: High 32-bit PCI address and data multiplexed pins.
During an address phase (when using the DAC command or when
REQ64B is asserted), the upper 32-bits of a 64-bit address are
transferred; otherwise, these bits are reserved, and are stable and
indeterminate. During a data phase, an additional 32-bits of data are
transferred when a 64-bit transaction has been negotiated by the
assertion of REQ64B and ACK64B.
PCI bus command and byte enables multiplexed pins. During the
address phase of a transaction, C/BE3-0 define the bus command.
During the data phase, C/BE3-0 are used as Byte Enables. The Byte
Enables are valid for the entire data phase and determine which byte
lanes carry meaningful data. C/BE0 applies to byte 0, and C/BE3
applies to byte 3.
During an address phase (when using DAC commands or when
REQ64B is asserted), the actual bus command is transferred on
C/BE7-4; otherwise, these bits are reserved and indeterminate. During a
data phase, C/BE7-4 are Byte Enables indicating which byte lanes carry
meaningful data when a 64-bit transaction has been negotiated by the
assertion of REQ64B and ACK64B. C/BE4 applies to byte 4 and
C/BE7 applies to byte 7.
PCI clock: This clock input provides timing for all PCI transactions and
is input to the PCI device. Supports up to a 66MHz PCI clock.
Clock Run: This signal is used by the RTL8169 to request starting (or
speeding up) the clock, CLK. CLKRUNB also indicates the clock
status. For the RTL8169, CLKRUNB is an open drain output as well as
an input. The RTL8169 requests the central resource to start, speed up,
or maintain the interface clock by the assertion of CLKRUNB. For the
host system, it is an S/T/S signal. The host system (central resource) is
responsible for maintaining CLKRUNB asserted, and for driving it high
to the negated (deasserted) state.
Device Select: As a bus master, the RTL8169 samples this signal to
insure that a PCI target recognizes the destination address for the data
transfer. As a target, the RTL8169 asserts this signal low when it
recognizes its target address after FRAMEB is asserted.
Cycle Frame: As a bus master, this pin indicates the beginning and
duration of an access. FRAMEB is asserted low to indicate the start of a
bus transaction. While FRAMEB is asserted, data transfer continues.
When FRAMEB is deasserted, the transaction is in the final data phase.
As a target, the device monitors this signal before decoding the address
to check if the current transaction is addressed to it.
7
Description
RTL8169
Rev.1.21