Table of Contents
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FAST ETHERNET CONTROLLER
WITH POWER MANAGEMENT
1 Packet Transmission ................................................................................................................................................................ 2
1.1 Architecture........................................................................................................................................................................ 2
1.2 Transmit Descriptors .......................................................................................................................................................... 2
1.3 The Transmission Process .................................................................................................................................................. 3
1.4 Registers Involved.............................................................................................................................................................. 4
1.5 Software Issues................................................................................................................................................................... 4
1.7 Sample code ....................................................................................................................................................................... 5
2 Packet Reception ...................................................................................................................................................................... 6
2.1 Architecture........................................................................................................................................................................ 6
2.2 The Packet Header ............................................................................................................................................................. 7
2.3 The Transmission Process .................................................................................................................................................. 7
2.4 Registers Involved.............................................................................................................................................................. 7
2.5 Software Issues................................................................................................................................................................... 8
2.6 Configuration ..................................................................................................................................................................... 8
2.7 Sample Code ...................................................................................................................................................................... 9
3 Initialization............................................................................................................................................................................ 10
Additional Notes........................................................................................................................................................................ 10
This document is intended for use by the software engineer when programming for the Realtek RTL8100 series NIC controller
chips. Information pertaining to the hardware design of products using these chips is contained in a separate document.
Though every effort has been made to assure that this document is current and accurate, more information may have become
available subsequent to the production of this programming guide. In that event, please contact your Realtek representative for
additional information which can help in the development process.
2001/12/10
REALTEK SINGLE CHIP
RTL8100
PROGRAMMING GUIDE
1
RTL8100
Rev.1.0
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Related Manuals for Realtek RTL8100
Summary of Contents for Realtek RTL8100
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Page 1: Table Of Contents
Additional Notes..................................10 This document is intended for use by the software engineer when programming for the Realtek RTL8100 series NIC controller chips. Information pertaining to the hardware design of products using these chips is contained in a separate document. -
Page 2: Packet Transmission
1.1 Architecture The transmit path of the RTL8100 uses 4 descriptors, each descriptor with a fixed IO address offset. The 4 descriptors are used in a round-robin fashion. As a descriptor is written, PCI operations start and move packets in the memory which the descriptor specifies to the Transmit FIFO. -
Page 3: The Transmission Process
RTL8100 Descriptor Tx FIFO TSAD0 TSD0 TSAD1 TSD1 TSAD2 TSD2 TSAD3 TSD3 1.3 The Transmission Process The following process describes the transmission of a packet. 1. The packet is copied to a physically continuous buffer in memory. 2. The appropriate descriptor is written as follows. -
Page 4: Registers Involved
RTL8100 1.4 Registers Involved 1. TSAD0-3 2. TSD0-3 3. ISR (TOK,TER),IMR (TOK,TER) 4. TCR: Transmit Configuration register 5. TSAD: Reflects the corresponding bits in the TSD0-3. 1.5 Software Issues This section covers the handling of Interrupts. When the driver is processing a transmit interrupt, the following two cases should be managed properly. -
Page 5: Sample Code
RTL8100 1.7 Sample Code unsigned char NextDesc( unsigned char CurrentDescriptor // (CurrentDescriptor == TX_SW_BUFFER_NUM-1) ? 0 : (1 + CurrentDescriptor); if(CurrentDescriptor == TX_SW_BUFFER_NUM-1) return 0; else return ( 1 + CurrentDescriptor); unsigned char CheckTSDStatus( unsigned char Desc ULONG Offset = Desc << 2;... -
Page 6: Packet Reception
2.1 Architecture The receive path of the RTL8100 is designed as a ring buffer. This ring buffer is a physical continuous memory structure. Data coming from the line is first stored in a Receive FIFO in the chip, and then moved to the receive buffer when the early receive threshold is met. -
Page 7: The Packet Header
RTL8100 2.2 The Packet Header Symbol Description Multicast Address Received: This bit set to 1 indicates that a multicast packet is received. Physical Address Matched: This bit set to 1 indicates that the destination address of this packet matches the value written in ID registers. -
Page 8: Software Issues
1024 bytes. When WRAP is enabled, the RTL8100 will move the reset of the packet data immediately after the buffer. This will make the last packet in the buffer continuous. However, the Receive buffer has to leave 1.5k additional space for this packet. -
Page 9: Sample Code
RTL8100 2.7 Sample Code BOOLEAN PacketOK( PPACKETHEADER pPktHdr BOOLEAN BadPacket = pPktHdr->RUNT || pPktHdr->LONG || pPktHdr->CRC || pPktHdr->FAE; if( ( !BadPacket ) && ( pPktHdr->ROK ) ) if ( (pPktHdr->PacketLength > RX_MAX_PACKET_LENGTH ) || (pPktHdr->PacketLength < RX_MIN_PACKET_LENGTH ) ) return(FALSE);... -
Page 10: Initialization
2. To enable source code debugging under Softice, the compiling/linking process needs to generate a ‘.map. file. Softice provide a ‘msym’ program to translate ‘.map’ files to ‘.sym’ files. After the ‘.sym’ file is generated, load the demo program with ‘Ldr demo’. Realtek Semiconductor Corp. Headquarters 1F, No. 2, Industry East Road IX, Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C.