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Realtek RTL8169 Manual

Gigabit ethernet media access controller with power management
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ETHERNET MEDIA ACCESS
WITH POWER MANAGEMENT
1. Features........................................................................ 2
2. General Description .................................................... 3
3. Block Diagram............................................................. 4
4. Pin Assignments .......................................................... 5
5. Pin Description ............................................................ 6
5.2 PCI Interface .......................................................... 7
5.4 LED Interface....................................................... 10
5.5 GMII, TBI, PHY CP ............................................ 10
5.6 Clock and NC Pins............................................... 12
5.7 Power Pins ........................................................... 12
6. Register Descriptions ................................................ 13
6.2 FLASH: Flash Memory Read/Write .................... 16
6.3 ERSR: Early Rx Status......................................... 16
6.4 Command ............................................................. 17
6.5 TPPoll: Transmit Priority Polling......................... 17
6.6 Interrupt Mask...................................................... 18
6.7 Interrupt Status..................................................... 19
6.8 Transmit Configuration ........................................ 20
6.9 Receive Configuration ......................................... 21
6.11 CONFIG 0.......................................................... 23
6.12 CONFIG 1.......................................................... 24
6.13 CONFIG 2.......................................................... 25
6.14 CONFIG 3.......................................................... 25
6.15 CONFIG 4.......................................................... 26
6.16 CONFIG 5.......................................................... 27
6.17 Multiple Interrupt Select .................................... 28
6.18 PHYAR: PHY Access ........................................ 28
6.24 C+CR: C+ Command......................................... 31
6.26 ETThR: Early Transmit Threshold..................... 31
6.27 Function Event ................................................... 32
6.28 Function Event Mask ......................................... 32
6.29 Function Preset State.......................................... 33
6.30 Function Force Event ......................................... 33
7.1 EEPROM Registers.............................................. 35
8. PCI Configuration Space Registers......................... 36
8.1 PCI Bus Interface ................................................. 36
8.1.1 Byte Ordering ............................................... 36
8.1.2 Interrupt Control........................................... 36
8.1.3 Latency Timer............................................... 36
8.1.4 64-Bit Data Operation .................................. 37
8.1.5 64-Bit Addressing......................................... 37
8.2 Bus Operation ...................................................... 37
2002/03/27
REALTEK GIGABIT
CONTROLLER
RTL8169
8.2.1 Target Read................................................... 37
8.2.2 Target Write.................................................. 38
8.2.3 Master Read.................................................. 38
8.2.4 Master Write................................................. 39
8.2.5 Configuration Access ................................... 40
8.3 Packet Buffering .................................................. 40
8.3.1 Transmit Buffer Manager ............................. 40
8.3.2 Receive Buffer Manager............................... 40
8.3.3 Packet Recognition....................................... 40
8.4 PCI Configuration Space Table............................ 41
8.7 Power Management functions.............................. 47
8.8 Vital Product Data (VPD) .................................... 49
9. Functional Description ............................................. 50
9.1 Transmit & Receive Operations........................... 50
9.1.1 Transmit........................................................ 50
9.1.2 Receive ......................................................... 55
9.2 Loopback Operation............................................. 58
9.3 Collision............................................................... 58
9.4 Flow Control ........................................................ 58
9.4.1. Control Frame Transmission ....................... 58
9.4.2. Control Frame Reception ............................ 58
9.5 Memory Functions ............................................... 59
9.5.1 Memory Read Line (MRL) .......................... 59
9.5.2 Memory Read Multiple (MRM) ................... 59
9.5.4 Dual Address Cycle (DAC).......................... 60
9.6 LED Functions ..................................................... 61
9.6.1 Link Monitor ................................................ 61
9.6.2 Rx LED ........................................................ 61
9.6.3 Tx LED......................................................... 62
9.6.4 Tx/Rx LED ................................................... 62
9.6.5 LINK/ACT LED........................................... 63
9.7 Physical Layer Interfaces ..................................... 64
9.7.3 Ten Bit Interface (TBI)................................. 64
10. Application Diagrams............................................. 65
10.1 10/100/1000Base-T Application ........................ 65
10.2 1000Base-X Application.................................... 65
11. Electrical Characteristics ....................................... 66
11.1 Temperature Limit Ratings................................. 66
11.2 DC Characteristics ............................................. 66
11.3 AC Characteristics ............................................. 67
11.3.1 FLASH/BOOT ROM Timing..................... 67
11.3.3 PCI Bus Operation Timing ......................... 70
11.3.4 MII Timing ................................................. 87
11.3.5 GMII Timing .............................................. 89
11.3.6 TBI Timing ................................................. 90
12. Mechanical Dimensions .......................................... 91
1
RTL8169
Rev.1.21

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  • Page 1: Table Of Contents

    RTL8169 REALTEK GIGABIT ETHERNET MEDIA ACCESS CONTROLLER WITH POWER MANAGEMENT RTL8169 1. Features................ 2 8.2.1 Target Read........... 37 2. General Description ............ 3 8.2.2 Target Write..........38 3. Block Diagram............. 4 8.2.3 Master Read..........38 4. Pin Assignments ............5 8.2.4 Master Write..........

  • Page 2: Features

    93C56 memory space or I/O space mapped data (128*16-bit EEPROM) to store resource configuration, transfers of the RTL8169 operational registers ID parameter, and VPD data. The 93C56 can also be Supports PCI VPD (Vital Product Data) used to store the CIS data structure for CardBus...

  • Page 3: General Description

    The PCI specification is inherently little-endian. The RTL8169 contains the ability to do little-endian to big-endian swaps. It is also possible that the RTL8169 can be used as a basis for a RISC CPU platform which expect the data to be in a big-endian format.

  • Page 4: Block Diagram

    RTL8169 3. Block Diagram Boot ROM EEPROM LED Driver Interface Interface Power Control Logic Early Interrupt Threshold Interrupt Register Control Logic Early Interrupt Control Logic Transmit/ FIFO Receive FIFO Control Logic Logic Interface 2002/03/27 Rev.1.21...

  • Page 5: Pin Assignments

    RTL8169 4. Pin Assignments VDD33 RSTPHYB TBILBK ROMCSB TXD7 TXD6 TXD5 TXD4 TXD3 TXD2 TXD1 VDD18 TXD0 TXEN LED0 VDD33 GTXCLK LED1 LED2 TXCLK LED3 VDD33 MA16 MA15 MA14 RXER MA13 RXCLK1 MA12 RXCLK MA11 RXDV MA10 RXD0 RXD1 RXD2...

  • Page 6: Pin Description

    RTL8169 to request a change in its current power management state and/or to indicate that a power management event has occurred. ISOLATEB Isolate Pin: Active low. Used to isolate the RTL8169 from the PCI bus. (ISOLATE#) The RTL8169 does not drive its PCI outputs (excluding PME#) and does not sample its PCI input (including RST# and PCICLK) as long as the Isolate pin is asserted.

  • Page 7: Pci Interface

    PCI device. Supports up to a 66MHz PCI clock. CLKRUNB Clock Run: This signal is used by the RTL8169 to request starting (or speeding up) the clock, CLK. CLKRUNB also indicates the clock status. For the RTL8169, CLKRUNB is an open drain output as well as an input.
  • Page 8 Initiator Ready: This indicates the initiating agent’s ability to complete the current data phase of the transaction. As a bus master, this signal will be asserted low when the RTL8169 is ready to complete the current data phase transaction. This signal is used in conjunction with the TRDYB signal.

  • Page 9: Flash/Bootprom/Eeprom/Mii Interface

    SERRB System Error: If an address parity error is detected and Configuration Space Status register bit 15 (detected parity error) is enabled, the RTL8169 asserts the SERRB pin low and bit 14 of Status register in Configuration Space. STOPB S/T/S Stop: Indicates that the current target is requesting the master to stop the current transaction.

  • Page 10: Led Interface

    Transmit Enable: In GMII mode (or MII mode), the assertion of TxEN Tx[9] indicates that the RTL8169 is presenting data on the GMII (or MII) for transmission. TxEn is asserted synchronously with the first octet (or nibble) of the preamble and remains asserted while all octets (or nibbles) to be transmitted are presented to the GMII (or MII).
  • Page 11 PHY to indicate the detection of a collision on the twisted pair medium, and remains asserted while the collision condition persists. In full duplex mode, this pin’s status is ignored by the RTL8169. The COL transitions asynchronously with respect to RxCLK, GTxCLK, or TxCLK.

  • Page 12: Clock And Nc Pins

    MDIO is driven and sampled synchronously with respect to MDC. In TBI mode, this pin is a reserved pin. TBILBK TBI LoopBack: The RTL8169 asserts this pin high when the TBI is in loopback mode. RSTPHYB PHY Reset pin: An active low signal used by the RTL8169 to force hardware reset to external PHYceiver at initial power-on.

  • Page 13: Register Descriptions

    RTL8169 6. Register Descriptions The RTL8169 provides the following set of operational registers mapped into PCI memory space or I/O space. Offset Description 0000h IDR0 ID Register 0: The ID registers 0-5 are only permitted to write by 4-byte access. Read access can be byte, word, or double word access.
  • Page 14 RTL8169 0055h CONFIG4 Configuration Register 4 0056h CONFIG5 Configuration Register 5 0057h Reserved R /W 0058h-005Bh TimerInt Timer Interrupt Register: Once having written a nonzero value to this register, the Timeout bit of ISR register will be set whenever the TCTR reaches to this value.

  • Page 15: Dtccr: Dump Tally Counter Command

    TxUndrn 16-bit counter of Tx underrun and discard packets (only possible on jumbo frames). Reserved Command: When set, the RTL8169 begins dumping 13 Tally counters to the address specified above. When this bit is reset by the RTL8169, the dumping has been completed.

  • Page 16: Flash: Flash Memory Read/Write

    Early Rx OK: The power-on value is 0. It is set when the Rx byte count of the arriving packet exceeds the Rx threshold. After the whole packet is received, the RTL8169 will set ROK or RER in ISR and clear this bit simultaneously. Setting this bit will invoke a ROK interrupt.

  • Page 17: Command

    Symbol Description Reserved Reset: Setting this bit to 1 forces the RTL8169 into a software reset state which disables the transmitter and receiver, reinitializes the FIFOs, and resets the system buffer pointer to the initial value (the start address of each descriptor group set in TNPDS, THPDS and RDSAR registers).

  • Page 18: Interrupt Mask

    RTL8169 6.6 Interrupt Mask (Offset 003Ch-003Dh, R/W) Symbol Description SERR System Error Interrupt: 1: Enable; 0: Disable. TimeOut Time Out Interrupt: 1: Enable; 0: Disable. 13:10 Reserved Reserved SWInt Software Interrupt: 1: Enable; 0: Disable. Tx Descriptor Unavailable Interrupt: 1: Enable; 0: Disable.

  • Page 19: Interrupt Status

    (Offset 003Eh-003Fh, R/W) Symbol Description SERR System Error: This bit is set to 1 when the RTL8169 signals a system error on the PCI bus. TimeOut Time Out: This bit is set to 1 when the TCTR register reaches the value of the TimerInt register.

  • Page 20: Transmit Configuration

    The digital loopback function is independent of the current link status. For analog loopback tests, software must force the external phyceiver into loopback mode while the RTL8169 operates normally. 00 : Normal operation 01 : Digital loopback mode...

  • Page 21: Receive Configuration

    23:17 Reserved RER8 When this bit is set to 1, the RTL8169 will calculate the CRC of any received packed with a length larger than 8 bytes. When this bit is cleared, the RTL8169 only calculates the CRC of any received packet with a length larger than 64-bytes.
  • Page 22 RTL8169 10:8 MXDMA2, 1, 0 Max DMA Burst Size per Rx DMA Burst: This field sets the maximum size of the receive DMA data bursts according to the following table: 000 = Reserved 001 = Reserved 010 = 64 bytes...

  • Page 23: 9346Cr: 93C46 (93C56) Command

    RTL8169 6.10 9346CR: 93C46 (93C56) Command (Offset 0050h, R/W) Symbol Description EEM1-0 Operating Mode: These 2 bits select the RTL8169 operating mode. EEM1 EEM0 Operating Mode Normal (RTL8169 network/host communication mode) Auto-load: Entering this mode will make the RTL8169 load the contents of the 93C46 (93C56) as when the RSTB signal is asserted.

  • Page 24: Config 1

    Driver Load: Software maybe use this bit to make sure that the driver has been loaded. Writing 1 is 1. Writing 0 is 0. When the command register bits IOEN, MEMEN, BMEN of PCI configuration space are written, the RTL8169 will clear this bit automatically.

  • Page 25: Config 2

    Magic Magic Packet: This bit is valid when the PWEn bit of CONFIG1 register is set. The RTL8169 will assert the PMEB signal to wakeup the operating system when the Magic Packet is received. Once the RTL8169 has been enabled for Magic Packet wakeup and has...

  • Page 26: Config 4

    LinkUp Link Up: This bit is valid when the PWEn bit of the CONFIG1 register is set. The RTL8169, in an adequate power state, will assert the PMEB signal to wakeup the operating system when the cable connection is reestablished.

  • Page 27: Config 5

    1: The PME_Status bit can be reset by PCI reset or by software. 0: The PME_Status bit can only be reset by software. Bit1 and bit0 are auto-loaded from the EEPROM Config5 byte to the RTL8169 Config5 register. 2002/03/27 Rev.1.21...

  • Page 28: Multiple Interrupt Select

    Reserved 11:0 MISR11-0 Multiple Interrupt Select: Indicates that the RTL8169 will make a receive interrupt after the RTL8169 has transferred the data bytes specified in this register into the system memory. If the value of this register is zero, there will be no early receive interrupts before the whole received packet is transferred to system memory.

  • Page 29: Tbi_Anar: Tbi Auto-Negotiation Advertisement

    RTL8169 6.20 TBI_ANAR: TBI Auto-Negotiation Advertisement (Offset 0068h-0069h, R/W) Symbol Description 15:14 Reserved. Always 0. 13:12 RF2, RF1 Remote Fault Bits: These 2 bits indicate that a fault or error condition has occurred. The default value is 00. Description No error, link Ok (default)

  • Page 30: Phystatus: Phy(Gmii Or Tbi) Status

    RTL8169 PS2(ASM_DIR), Asymmetric Pause: When this bit is set, the value of bit7 (Pause) PS1(PAUSE) indicates the direction that PAUSE frames are supported by the link partner. Capability No Pause. Asymmetric PAUSE toward link partner. Symmetric PAUSE. Both symmetric PAUSE and asymmetric PAUSE toward local device.

  • Page 31: C+Cr: C+ Command

    Receive VLAN De-tagging Enable: 1: Enable; 0: Disable. RxChkSum Receive Checksum Offload Enable: 1: Enable; 0: Disable. PCI Dual Address Cycle Enable: When set, the RTL8169 will perform Tx/Rx DMA using PCI Dual Address Cycle only when the High 32-bit buffer address is not equal to 0.

  • Page 32: Function Event

    RTL8169 6.27 Function Event (Offset 00F0h-00F3h, R/W) Symbol Description 31:16 Reserved INTR Interrupt: This bit is set to 1 when the INTR field in the Function Force Event Register is set. Writing a 1 may clear this bit. Writing a 0 has no effect.

  • Page 33: Function Preset State

    RTL8169 6.29 Function Preset State (Offset 00F8h-00FBh, R) Symbol Description 31:16 Reserved INTR Interrupt: This bit is set when one of the ISR register bits has been set to 1. This bit remains set (1), until all of the ISR register bits have been cleared.

  • Page 34: Eeprom (93C46 Or 93C56) Contents

    7. EEPROM (93C46 or 93C56) Contents The RTL8169 supports the attachment of an external EEPROM. The 93C46 is a 1K-bit EEPROM, and the 93C56 is a 2K-bit EEPROM. The EEPROM interface provides the ability for the RTL8169 to read from and write data to an external serial EEPROM device.

  • Page 35: Eeprom Registers

    RTL8169 20h-2Fh Reserved 30h-31h CISPointer Reserved: Do not change this field without Realtek approval. CIS Pointer. 32h-33h CheckSum Reserved: Do not change this field without Realtek approval. Checksum of the EEPROM content. 34h-3Eh Reserved: Do not change this field without Realtek approval.

  • Page 36: Pci Configuration Space Registers

    ENDIAN bit of the C+ Command Register. When the RTL8169 is configured in big-endian mode, all the data in the data phase of either memory or I/O transaction to or from RTL8169 is in big-endian mode. All data in the data phase of any PCI configuration transaction to the RTL8169 should be in little-endian mode, regardless if the RTL8169 is set to big-endian or little-endian mode.

  • Page 37: 64-Bit Data Operation

    TRDYB will be forced HIGH on the next clock for 1 cycle, and then tri-stated. If FRAMEB is asserted beyond the assertion of IRDYB, the RTL8169 will still make data available as described above, but will also issue a Disconnect. That is, it will assert the STOPB signal with TRDYB. STOPB will remain asserted until FRAMEB is detected as deasserted.

  • Page 38: Target Write

    On the 2nd cycle after the assertion of DEVSELB, the device will monitor the IRDYB signal. If IRDYB is asserted at that time, the RTL8169 will assert TRDYB. On the next clock the 32-bit double word will be latched in, and TRDYB will be forced HIGH for 1 cycle and then tri-stated.

  • Page 39: Master Write

    8.2.4 Master Write A Master Write operation starts with the RTL8169 asserting REQB. If GNTB is asserted within 2 clock cycles, FRAMEB, Address, and Command will be generated 2 clocks after REQB (Address and FRAMEB for 1 cycle only). If GNTB is asserted 3 cycles or later, FRAMEB, Address, and Command will be generated on the clock following GNTB.

  • Page 40: Configuration Access

    FIFO from the MAC unit before a DMA request for system memory occurs. Once the RTL8169 gets the bus, it will continue to transfer the long words from the FIFO until the data in the FIFO is less than one long word, or has reached the end of the packet, or the max DMA burst size is reached , as set in MXDMA.

  • Page 41: Pci Configuration Space Table

    RTL8169 8.4 PCI Configuration Space Table Name Type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VID15 VID14 VID13 VID12 VID11 VID10 VID9 VID8 DID7 DID6 DID5 DID4 DID3 DID2 DID1 DID0...

  • Page 42: Pci Configuration Space Functions

    This bit’s state after RST# is 0. SERREN System Error Enable: When set to 1, the RTL8169 asserts the SERRB pin when it detects a parity error on the address phase (AD<31:0> and CBEB<3:0> ).
  • Page 43 BMEN Bus Master Enable: When set to 1, the RTL8169 is capable of acting as a PCI bus master. When set to 0, it is prohibited from acting as a bus master. For normal operations, this bit must be set by the system BIOS.
  • Page 44 RTL8169 SCR: Sub-Class Register The Sub-class register is an 8-bit register that identifies the function of the RTL8169. SCR = 00h indicates that the RTL8169 is an Ethernet controller. BCR: Base-Class Register The Base-class register is an 8-bit register that broadly classifies the function of the RTL8169. BCR = 02h indicates that the RTL8169 is a network controller.
  • Page 45 MXLAT: Maximum Latency Timer: Read only Specifies how often the RTL8169 needs to gain access to the PCI bus in unit of 1/4 microsecond. This field will be set to a value from the external EEPROM. If there is no EEPROM, this field will default to a value of 20h.

  • Page 46: Default Value After Power-On (Rstb Asserted)

    RTL8169 8.6 Default Value After Power-on (RSTB Asserted) PCI Configuration Space Table Name Type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Command PERRSP MWIEN BMEN MEMEN IOEN SERREN Status NewCap DPERR SSERR RMABT RTABT STABT Revision ID PIFR LTR7...

  • Page 47: Power Management Functions

    RTL8169 provides the following capabilities: The RTL8169 can monitor the network for a Wakeup Frame, a Magic Packet, or a Re-LinkOk, and notify the system via PME# when such a packet or event occurs. Then, the whole system can be restore to a working state to process the incoming jobs.
  • Page 48 RTL8169 to stop asserting a PME# (if enabled). When the RTL8169 is in power down mode, ex. D1-D3, the IO, MEM, and Boot ROM spaces are all disabled, after a RST# assertion, the RTL8169’s power state is restored to D0 automatically, if the original power state is D3 .

  • Page 49: Vital Product Data (Vpd)

    Reset the flag bit to 0 at the same time the VPD address is written to retrieve VPD data from EEPROM. When the flag bit is set to 1 by the RTL8169, the VPD data (4 bytes per VPD access) has been transferred from EEPROM to the VPD data register.

  • Page 50: Functional Description

    Software must pre-allocate enough buffers and configure all descriptor rings before transmitting and/or receiving packets. Descriptors can be chained to form a packet in both Tx and Rx. Please refer to the Realtek RTL8169 programming guide for detailed information. Any Tx buffers pointed to by one of Tx descriptors should be at least 4 bytes.
  • Page 51 RTL8169 Large-Send Task Offload Tx Descriptor Format (before transmitting, OWN=1, LGSEN=1, Tx command mode 0) 31 30 29 28 27 26 16 15 8 7 6 5 4 3 Large-Send MSS value Offset 0 (11 bits) Frame_Length VLAN_TAG Offset 4...
  • Page 52 RTL8169 TAGC VLAN tag control bit: 1: Enable; 0: Disable. 1: Add TAG. 0x8100 (Ethernet encoded tag protocol ID, indicating that this is a IEEE 802.1Q VLAN packet) is inserted after source address, and 2 bytes are inserted after tag protocol ID from VLAN_TAG field in transmit descriptor.
  • Page 53 RTL8169 Offset# Bit# Symbol Description Ownership: This bit, when set, indicates that the descriptor is owned by the NIC, and that the data relative to this descriptor is ready to be transmitted. When cleared, it indicates that the descriptor is owned by the host system.
  • Page 54 RTL8169 Tx Status Descriptor (after transmitting, OWN=0, Tx status mode) After having transmitted, the Tx descriptor turns into a Tx status descriptor. 31 30 29 28 27 26 16 15 8 7 6 5 4 3 RSVD Offset 0 RSVD...

  • Page 55: Receive

    RTL8169 15:0 VLAN_TAG VLAN Tag: The 2-byte VLAN_TAG contains information, from the upper layer, of user priority, canonical format indicator, and VLAN ID. Please refer to IEEE 802.1Q for more VLAN tag information. VIDH: The high 4 bits of a 12-bit VLAN ID.
  • Page 56 IEEE802.1Q VLAN TAG (0x8100) available packet. 15:0 VLAN_TAG VLAN Tag: If the TAG of the packet is 0x8100, The RTL8169 MAC extracts four bytes from after source ID, sets the TAVA bit to 1, and moves the TAG value of this field in Rx descriptor.
  • Page 57 Physical Address Matched: This bit, when set, indicates that the destination address of this Rx packet matches the value in the RTL8169’s ID registers. Broadcast Address Received: This bit, when set, indicates that a broadcast packet has been received. BAR and MAR will not be set simultaneously.

  • Page 58: Loopback Operation

    9.3 Collision If the RTL8169 is not in full-duplex mode, a collision event occurs when the receive input is not idle while the RTL8169 transmits. If the collision was detected during the preamble transmission, a jam pattern is transmitted after completing the preamble (including the JK symbol pair when network speed is 100Mbps).

  • Page 59: Memory Functions

    The Memory Read Line (MRL) command operates in conjunction with the Memory Read Multiple command (MRM). iv. The RTL8169 will terminate the read transaction on the cache line boundary when it is out of resources on the transmit DMA. For example, when the transmit FIFO is almost full.

  • Page 60: Memory Write And Invalidate (Mwi)

    The Dual Address Cycle (DAC) command is used to transfer a 64-bit address to devices that support 64-bit addressing when the address is not in the low 4 GB address space. The RTL8169 is capable of performing DAC, such that it is very competent as a network server card in a heavy-duty server with the possibility of allocating a memory buffer above a 4GB memory address space.

  • Page 61: Led Functions

    RTL8169 9.6 LED Functions The RTL8169 supports 4 LED signals in 4 different configurable operation modes. The following sections describe the different LED actions. 9.6.1 Link Monitor The Link Monitor senses the link integrity or if a station is down, such as LINK10, LINK100, LINK1000, LINK10/100/1000, LINK10/ACT, LINK100/ACT, or LINK1000/ACT.

  • Page 62: Tx Led

    RTL8169 9.6.3 Tx LED In 10/100/1000Mbps mode, blinking of the Tx LED indicates that transmit activity is occurring. Power On LED = High Transmitting Packet? LED = High for (100 +- 10) ms LED = Low for (12 +- 2) ms 9.6.4 Tx/Rx LED...

  • Page 63: Link/Act Led

    RTL8169 9.6.5 LINK/ACT LED In 10/100/1000Mbps mode, blinking of the LINK/ACT LED indicates that the RTL8169 is linked and operating properly. This LED high for extended periods, indicates that a link problem exists. Power On LED = High Link? LED = Low...

  • Page 64: Physical Layer Interfaces

    RTL8169 also supports TBI (Ten-Bit Interface) for 1000Base-X applications by connecting to industry standard external SERDES devices for fiber applications. The RTL8169 only operates in full-duplex mode in 1000Mbps for both GMII and TBI applications. In addition, a management interface is defined for MII and GMII.

  • Page 65: Application Diagrams

    RTL8169 10. Application Diagrams 10.1 10/100/1000Base-T Application Main/Aux. Power Power 3.3V, 2.5V, 1.8V Regulators Power 3.3V, 1.8V Power 3.3V Power 3.3V, 2.5V, 1.8V BootROM / FLASH GMII Power 3.3V RTL8169 External PHY - Marvell 88E1000 EEPROM 125MHz clock 25MHz clock...

  • Page 66: Electrical Characteristics

    Minimum Maximum Units °C Storage temperature +125 °C Operating temperature 11.2 DC Characteristics Below is a description of the general DC specifications for the RTL8169. Symbol Parameter Conditions Minimum Typical Maximum Units VDD33 3.3V Supply Voltage VDD18 1.8V Supply Voltage 1.71...

  • Page 67: Ac Characteristics

    RTL8169 11.3 AC Characteristics 11.3.1 FLASH/BOOT ROM Timing FLASH/BOOT ROM - Read MA16-0 ROMCSB TWRBR TOES TOHZ TOOLZ TCOLZ MD7-0 TACC Symbol Description Minimum Typical Maximum Units Read Cycle Chip Enable Access Time TACC Address Access Time TOES Output Enable Access Time...
  • Page 68 RTL8169 FLASH MEMORY - Write SETUPMPROGRAM COMMAND PROGRAM COMMAND STANDBY/VCC PROGRAM VERIFY VCC POWER-UP LATCH ADDRESS POWER-DOWN PROGRAMMING VERIFICATION COMMAND & STANDBY & DATA MA16-0 ROMCSB tWHWH1 tWHGL tWPH tGHWL tOOLZ VALID DATAOUT DATAOUT DATAO MD7-0 DATA =40H =C0H tCOLZ...

  • Page 69: Serial Eeprom Interface Timing

    RTL8169 11.3.2 Serial EEPROM Interface Timing (93C46(64*16)/93C56(128*16)) EESK EECS EEDI (Read) (Read) EEDO High Impedance EESK EECS EEDI (Write) (Write) EEDO BUSY READY High Impedance EESK tskh tskl tcsh EECS tcss tdis tdih EEDI tdos tdoh EEDO (Read) EEDO STATUS VALID...

  • Page 70: Pci Bus Operation Timing

    RTL8169 11.3.3 PCI Bus Operation Timing PCI Bus Timing Parameters 66MHz 33MHz Symbol Parameter Units T val CLK to Signal Valid Delay-bused signals T val(ptp) CLK to Signal Valid Delay-point to point T on Float to Active Delay T off...
  • Page 71 RTL8169 PCI Clock Specification T_high T_low 0.6Vcc 0.5Vcc 0.4Vcc, peak-to-peak 0.4Vcc (minimum) 0.3Vcc 0.2Vcc T_cyc 3.3V Clock Waveform V_ih V_test CLK (@ Device #1) T_skew V_il T_skew V_ih T_skew V_test CLK (@ Device #2) V_il Clock Skew Diagram 66MHz 33MHz...
  • Page 72 RTL8169 PCI Transactions FRAMEB AD31-0 ADDRESS DATA C/BE3-0B BUS CMD BE3-0B IRDYB TRDYB DEVSELB I/O Read FRAMEB AD31-0 ADDRESS DATA C/BE3-0B BUS CMD BE3-0B IRDYB TRDYB DEVSELB Fig. 11.3.3.3.2 I/O Write 2002/03/27 Rev.1.21...
  • Page 73 RTL8169 FRAMEB IDSEL AD31-0 ADDRESS DATA C/BE3-0B BUS CMD BE3-0B IRDYB TRDYB DEVSELB Configuration Read FRAMEB IDSEL AD31-0 ADDRESS DATA C/BE3-0B BUS CMD BE3-0B IRDYB TRDYB DEVSELB Configuration Write 2002/03/27 Rev.1.21...
  • Page 74 RTL8169 REQB-A REQB-B GNTB-A GNTB-B FRAMEB ADDRESS DATA ADDRESS DATA BUS Arbitration FRAMEB AD31-0 ADDRESS DATA-1 DATA-2 DATA-3 C/BE3-0B BUS CMD BE3-0B IRDYB TRDYB DEVSELB Memory Read below 4GB (32-bit address, 32-bit data; 32-bit slot) 2002/03/27 Rev.1.21...
  • Page 75 RTL8169 FRAMEB AD31-0 ADDRESS DATA-1 DATA-2 DATA-3 C/BE3-0B BUS CMD BE3-0B-1 BE3-0B-2 BE3-0B-3 IRDYB TRDYB DEVSELB Memory Write below 4GB (32-bit address, 32-bit data; 32-bit slot) 2002/03/27 Rev.1.21...
  • Page 76 RTL8169 FRAMEB REQ64B AD31-0 ADDRESS DATA-1 DATA-2 DATA-3 AD63-32 C/BE3-0B BUS CMD BE3-0B C/BE7-4B BE7-4B IRDYB TRDYB DEVSELB ACK64B Memory Read below 4GB (32-bit address, 32-bit data transfer granted; 64-bit slot) 2002/03/27 Rev.1.21...
  • Page 77 RTL8169 FRAMEB REQ64B AD31-0 ADDRESS DATA-1 DATA-2 DATA-3 AD63-32 DATA-2 C/BE3-0B BUS CMD BE3-0B-1 BE3-0B-2 BE3-0B-3 C/BE7-4B BE7-4B-1 IRDYB TRDYB DEVSELB ACK64B Memory Write below 4GB (32-bit address, 32-bit data transfer granted; 64-bit slot) 2002/03/27 Rev.1.21...
  • Page 78 RTL8169 FRAMEB REQ64B AD31-0 ADDRESS DATA-1 DATA-3 DATA-5 AD63-32 DATA-2 DATA-4 DATA-6 C/BE3-0B BUS CMD BE3-0B C/BE7-4B BE7-4B IRDYB TRDYB DEVSELB ACK64B Memory Read below 4GB (32-bit address, 64-bit data transfer granted; 64-bit slot) 2002/03/27 Rev.1.21...
  • Page 79 RTL8169 FRAMEB REQ64B AD31-0 ADDRESS DATA-1 DATA-3 DATA-5 AD63-32 DATA-2 DATA-4 DATA-6 C/BE3-0B BUS CMD BE3-0B-1 BE3-0B-2 BE3-0B-3 C/BE7-4B BE7-4B-1 BE7-4B-2 BE7-4B-3 IRDYB TRDYB DEVSELB ACK64B Memory Write below 4GB (32-bit address, 64-bit data transfer granted; 64-bit slot) 2002/03/27 Rev.1.21...
  • Page 80 RTL8169 FRAMEB AD31-0 HI-ADDR LO-ADDR DATA-1 DATA-2 DATA-3 C/BE3-0B DAC CMD BUS CMD BE3-0B IRDYB TRDYB DEVSELB Memory Read above 4GB (DAC, 64-bit address, 32-bit data; 32-bit slot) FRAMEB AD31-0 LO-ADDR HI-ADDR DATA-1 DATA-2 DATA-3 C/BE3-0B BUS CMD BE3-0B-1 BE3-0B-2...
  • Page 81 RTL8169 FRAMEB REQ64B AD31-0 HI-ADDR LO-ADDR DATA-1 DATA-2 DATA-3 AD63-32 HI-ADDR C/BE3-0B DAC CMD BUS CMD BE3-0B C/BE7-4B BUS CMD BE7-4B IRDYB TRDYB DEVSELB ACK64B Memory Read above 4GB (DAC, 64-bit address, 32-bit data transfer granted; 64-bit slot) 2002/03/27 Rev.1.21...
  • Page 82 RTL8169 FRAMEB REQ64B AD31-0 LO-ADDR HI-ADDR DATA-1 DATA-2 DATA-3 AD63-32 HI-ADDR DATA-2 C/BE3-0B DAC CMD BUS CMD BE3-0B-1 BE3-0B-2 BE3-0B-3 C/BE7-4B BUS CMD BE7-4B-1 IRDYB TRDYB DEVSELB ACK64B Memory Write above 4GB (DAC, 64-bit address, 32-bit data transfer granted; 64-bit slot) 2002/03/27 Rev.1.21...
  • Page 83 RTL8169 FRAMEB REQ64B AD31-0 LO-ADDR HI-ADDR DATA-1 DATA-3 DATA-5 AD63-32 HI-ADDR DATA-2 DATA-4 DATA-6 C/BE3-0B DAC CMD BUS CMD BE3-0B C/BE7-4B BUS CMD BE7-4B IRDYB TRDYB DEVSELB ACK64B Memory Read above 4GB (DAC, 64-bit address, 64-bit data transfer granted; 64-bit slot) 2002/03/27 Rev.1.21...
  • Page 84 RTL8169 FRAMEB REQ64B AD31-0 LO-ADDR HI-ADDR DATA-1 DATA-3 DATA-5 AD63-32 HI-ADDR DATA-2 DATA-4 DATA-6 C/BE3-0B DAC CMD BUS CMD BE3-0B-1 BE3-0B-2 BE3-0B-3 C/BE7-4B BUS CMD BE7-4B-1 BE7-4B-2 BE7-4B-3 IRDYB TRDYB DEVSELB ACK64B Memory Write above 4GB (DAC, 64-bit address, 64-bit data transfer granted; 64-bit slot)
  • Page 85 RTL8169 FRAMEB IRDYB TRDYB STOPB DEVSELB Target Initiated Termination - Disconnect FRAMEB IRDYB TRDYB STOPB DEVSELB Target Initiated Termination - Abort 2002/03/27 Rev.1.21...
  • Page 86 RTL8169 FRAMEB IRDYB TRDYB NO RESPONSE DEVSELB FAST SLOW ACKNOWLEDGE Master Initiated Termination - Abort FRAMEB ADDRESS DATA ADDRESS DATA C/BE# BUS CMD BUS CMD PAR/PAR64 SERR# PERR# Parity Operation - One Example 2002/03/27 Rev.1.21...

  • Page 87: Mii Timing

    RTL8169 11.3.4 MII Timing MII Timing – MII PORT - Transmit tTxCC tTxCH Vih(min) TxCLK tTxCL Vil(max) tTxRV tTxHT Vih(min) TxD[3:0], TxEN Vil(max) MII Transmit Timing 10MHz 100MHz Symbol Description Units Typical Typical tTxCC Tx Clock Cycle tTxCH Tx Clock High Time...
  • Page 88 RTL8169 MII Timing – MII Management Port tMCC tMCH Vih(min) tMCL Vil(max) tMRV tMSU tMHT Vih(min) MDIO Vil(max) MII Management Timing Symbol Description Units Typical tMCC MDC Cycle Time tMCH MDC High Time tMCL MDC Low Time tMSU MDIO Setup Time...

  • Page 89: Gmii Timing

    RTL8169 11.3.5 GMII Timing tGCC tGCH Vih_ac(min) RxCLK, GTxCLK tGCL Vil_ac(max) tGSUT tGHTT tGSUR tGHTR RxD[7:0], RxDV, Vih_ac(min) RxER, TxD[7:0], TxEN Vil_ac(max) GMII Timing Symbol Description Typical Units Vil_ac Input Low Voltage ac Vih_ac Input High Voltage ac fGTxCLK, fRxCLK GTxCLK, RxCLK frequency...

  • Page 90: Tbi Timing

    RTL8169 11.3.6 TBI Timing tTxCC 2.0V GTxCLK 1.4V 0.8V tTxSU tTxHT 2.0V Tx[9:0] Valid Data 0.8V TBI Tx Timing tA-B RxCLK0 1.4V tRxSU tRxSU 2.0V Rx[9:0] 0.8V tRxHT tRxHT RxCLK1 1.4V TBI Rx Timing Symbol Description Typical Units tTxCC Tx Clock Cycle...

  • Page 91: Mechanical Dimensions

    1.169 1.205 1.240 29.70 30.60 31.50 VERSION 0.50 PAGE 22 OF 22 0.010 0.020 0.030 0.25 0.75 CHECK DWG NO. Q208 - 1 0.041 0.051 0.061 1.05 1.30 1.55 0.004 0.10 DATE APR. 11.1997 0° 12° 0° 12° REALTEK SEMICONDUCTOR CO., LTD Θ 2002/03/27 Rev.1.21...
  • Page 92 RTL8169 Realtek Semiconductor Corp. Headquarters 1F, No. 2, Industry East Road IX, Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Tel : 886-3-5780211 Fax : 886-3-5776047 WWW: www.realtek.com.tw 2002/03/27 Rev.1.21...

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