Vertical Preamplifier. Diode Gate. And Delay Line Driver. Simplified Block Diagram - Tektronix 2336YA Instruction Manual

Theory of Ope rat ion -2336 Service
Channel 1 Positioning
Hybrid circuit U55 provides balanced current sources
for producing at least * I 2 divisions of vertical positioning
for the displayed signal. POSITION control R903 varies
the amount of dc-offset current added t o the vertical signal
current at U55 pins
2 and 6. The sum of the dc-offset
current and the vertical-signal current establishes the
vertical position of the crt display. Diodes CR53 and CR54,
connected between U55 pins 2 and 6, limit the range of
the Channel 1 positioning circuit t o prevent it from
affecting the horizontal-display position when the X-Y
feature is in use. Corresponding diodes are not included
in the Channel 2 circuitry.
Channel 1 Common-Base Output Stage
A common-base output stage composed of Q55 and 0 5 7
provides current-summing nodes for the vertical positioning
and Channel 1 signal currents. When the TRIG VIEW
feature is used, the output o f the common-base stage is
blocked by a diode gate to prevent the vertical input signal
from reaching the Delay Line Driver.
-
Channel 2 Invert Operation
The Channel 2 common-base output stage is composed
of two transistor pairs. In the noninverting mode, tran-
sistors Q132 and Q134 are biased on to carry the signal
current. When the INVERT push-button switch is pressed
in, Q132 and Q134 become biased off; and Q133 and Q135
are biased on. The collectors of 0133 and 0135 are cross-
connected to the stage output points; consequently, the
Channel 2 signal current becomes inverted.
Diode Gates
Channel 1 Diode Gate is composed o f CR55, CR56,
CR57, and CR58. The Diode Gate acts as a switch that i s
CH 1
'TENUATOR
CH 1
PREAMP-
L I F I E R
1 ST
STAGE
VERTICAL
SIGNAL
TO DELAY
CH 1 TRIGGER
SIGNAL TO
TRIGGER
GENERATOR
PREAMPLIFIER
FROM
TRIGGER
GENERATOR
TRIG VIEW -
(TRI G
V I E W ENABLE
1
VERTICAL
SWITCHING VERT MODE TRIGGER ENABLE
LOGIC L
F
I
VERT MODE
TRIGGER
T 0
TRIGGER
GENERATOR
4 1 1 6-64
Figure
3-3.
Vertical Preamplifier, Diode Gate. and Delay Line Driver, simplified block diagram.