Watchdog Timer Operation When "Low-Speed Ring-Osc Can Be Stopped By Software" Is Selected By Option Byte - NEC 78K0S/KA1+ Preliminary User's Manual

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9.4.2
The operation clock of the watchdog timer can be selected as either the low-speed Ring-OSC clock or the clock to
peripheral hardware.
After reset is released, operation is started at the maximum cycle of the low-speed Ring-OSC clock (bits 2, 1, and 0
(WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1).
The following shows the watchdog timer operation after reset release.
1. The status after reset release is as follows.
• Operation clock: Low-speed Ring-OSC clock
• Cycle: f
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• Counting starts
2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation
instruction
• Operation clock: Any of the following can be selected using bits 3 and 4 (WDCS3 and WDCS4).
• Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)
3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.
Notes 1.
Caution In this mode, watchdog timer operation is stopped during HALT/STOP instruction execution.
For the watchdog timer operation during STOP mode and HALT mode in each status, see 9.4.3 Watchdog timer
operation in STOP mode and 9.4.4 Watchdog timer operation in HALT mode.
A status transition diagram is shown below.
Watchdog timer operation when "low-speed Ring-OSC can be stopped by software" is selected by
option byte
18
/2 (1.09 seconds: At operation with f
RL
Notes 1, 2, 3
.
Low-speed Ring-OSC clock (f
Clock to peripheral hardware (f
Watchdog timer operation stopped
As soon as WDTM is written, the counter of the watchdog timer is cleared.
2. Set bits 7, 6, and 5 to 0, 1, 1, respectively. Do not set the other values.
If the watchdog timer is stopped by setting WDCS4 and WDCS3 to 1 and ×, respectively, an internal
3.
reset signal is not generated even if the following processing is performed.
• WDTM is written a second time.
• A 1-bit memory manipulation instruction is executed to WDTE.
• A value other than ACH is written to WDTE.
After HALT/STOP mode is released, counting is started again using the operation clock of the
watchdog timer set before HALT/STOP instruction execution by WDTM. At this time, the counter
is not cleared to 0 but holds its value.
CHAPTER 9 WATCHDOG TIMER
= 240 kHz (TYP.))
RL
)
RL
)
XP
Preliminary User's Manual U16898EJ1V0UD
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