NEC 78K0S/KA1+ Preliminary User's Manual page 258

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Address: FF80H
7
1
RINGOSC
1
0
Cautions 1. If it is selected that low-speed Ring-OSC clock oscillation cannot be stopped, the count
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OSCSEL1
0
0
1
Caution Because the X1 and X2 pins are also used as the P121 and P122 pins, the conditions under
Remark
RMCE
1
0
Caution If a low level is input to the RESET pin after reset is released by the power-on clear function
258
CHAPTER 17 OPTION BYTE
Figure 17-2. Format of Option Byte (1/2)
6 5
DEFOSTS1 DEFOSTS0
Cannot be stopped
Can be stopped by software
clock to the watchdog timer (WDT) is fixed to low-speed Ring-OSC.
2. If it is selected that low-speed Ring-OSC can be stopped by software, supply of the count
clock to WDT is stopped in the HALT/STOP mode, regardless of the setting of bit 0
(LSRSTOP) of the low-speed Ring-OSC mode register (LSRCM). If low-speed Ring-OSC
is selected as the count clock to 8-bit timer H1, however, the count clock is supplied in
the HALT/STOP mode while low-speed Ring-OSC operates (LSRSTOP = 0).
OSCSEL0
0 Crystal/ceramic oscillation clock
1 External clock input
×
High-speed Ring-OSC clock
which the X1 and X2 pins can be used as port pins differ depending on the selected system
clock source.
(1) High-speed Ring-OSC clock
P121 and P122 can be used as I/O port pins.
(2) Crystal/ceramic oscillation clock
The X1 and X2 pins cannot be used as I/O port pins because they are used as clock input
pins.
(3) External clock input
Because the X1 pin is used as an external clock input pin, P121 cannot be used as an I/O
port pin.
× : don't care
RESET pin is used as is.
RESET pin is used as input port pin (P34).
and before the option byte is referenced again, the 78K0S/KA1+ is reset, and the status is
held until a high level is input to the RESET pin.
Preliminary User's Manual U16898EJ1V0UD
4 3
1 RMCE OSCSEL1
Low-speed Ring-OSC clock oscillation
Selection of system clock source
Control of RESET pin
2 1 0
OSCSEL0 RINGOSC