Block Diagram - NEC 78K0S/KA1+ Preliminary User's Manual

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1.6 Block Diagram

TO00/TI010/P31
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ANI0/P20 to
Note V
16-bit timer event
counter 00
TI000/P30
8-bit timer 80
TOH1/P42
8-bit timer H1
Low-speed
Ring-OSC
Watchdog timer
RxD6/P44
Serial interface
UART6
TxD6/P43
4
ANI3/P23
A/D converter
AV
REF
INTP0/P30
INTP1/P43
Interrupt control
INTP2/P31
INTP3/P41
and AV are internally connected in the 78K0S/KA1+. Be sure to connect V
SS SS
order to stabilize V via GND (= 0 V).
SS
CHAPTER 1 OVERVIEW
78K0S
Flash
CPU
memory
core
Internal
high-speed
RAM
Note
V V
DD SS
Preliminary User's Manual U16898EJ1V0UD
Port 2 4
P20 to P23
2
P30, P31
Port 3
P34
Port 4 6 P40 to P45
Port 12 3 P121 to P123
Port 13 P130
Power on clear/
POC/LVI
low voltage
control
indicator
Reset control
RESET/P34
System control
X1/P121
X2/P122
High-speed
Ring-OSC
to stabilized GND in
SS
17