Phase-Locked Loops (Plls); Receive Clocks - Vocality V200 User Manual

Vocality User Manual
User Manual for V200
Valid for V08_08.02 or V08_48.02

5.14.6 Phase-Locked Loops (PLLs)

All data ports have access to a pool of Phase-Locked Loops (PLLs) for the independent
derivation of RXC or TXC. The reference clock for the PLLs is derived from either the
GC1 or the GC2 global clock busses as selected on the ‡Data menu. The PLLs allow data
ports bit rates to be derived in steps as follows:
Min Max
25Hz 9600Hz
50 9600
10400 512000
520000 5120000
5128000 10240000
DBA rate changes are accomplished using logic which ensures no spikes or glitches on
the clock signal during the transition.

5.14.7 Receive Clocks

The RXC signal is selected from four possible modes:
EXT The external interface. In DCE mode, this clock comes from the TT pin. In DTE mode,
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Interval
25Hz
-
800Hz
8000Hz
8000Hz High Speed CPU card or BASICS IP only
Figure 5-44 Terminal timing signals
Table 5-7 PLL rates