2.11.5 Detector Mother Board Overview
2.11.6 Detector Mother Board Operation
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2-72 System Overview
The four fine gain control comparators are set up in two windows around the
High Energy signal. If the signal falls into the lower window a signal is sent to
the programmable logic (PLD). The PLD then sends an amplify signal to a
DAC which in turn increases gain slightly at the pulse shaping amplifier, so
that the High Energy Signal is +2.4 VDC. If the High Energy signal falls into
the upper window, the fine gain is adjusted down slightly by the same
mechanism at the pulse shaping amplifier, again so that the High Energy
Signal is + 2.4 VDC.
The fine gain adjust is applied to the entire signal on a particular channel at
the pulse shaping amplifier, therefore the Low Energy Signal's gain is
adjusted along with the High Energy Signal.
The 4 comparators of the Gain Stage are set by digital to analog converters
(DAC's) which use reference values stored in the Flash RAM of the Detector
Mother Board.
Energy Discrimination and Pulse Counting
The amplified and gain adjusted pulse is simultaneously fed to a second bank
of 4 comparators which are divided again into two sets of windows. The
windows of the Discrimination stage are centered around the High and Low
Energy pulses. These comparators are also set by DAC's which are set by the
DMB Flash RAM.
Each time a pulse falls into the High Energy window, a counter in the
programmable logic (PLD) is ticked, the same happens for the Low Energy
window. These two data signals are then passed to the DMB, which transmits
the data to the SBC.
• Contains 4 slots for the DDB's (see figure 2-9)
• Contains a slot for the Test Point Board (part of the PRODIGY tool kit see
figure 2-9)
• The Detector Mother Board provides +5 V, ±12 V plus digital and analog
grounds to the Detector Daughter Boards.
• The Detector Mother Board communicates with the SBC via RS-422 link.
• The patient positioning laser is controlled by the SBC via the DMB (See
figure 2-9).
The Detector Mother Board (DMB) contains a processor and Flash RAM,
which supplies programming data to the detector subsystem. The data for all
comparator settings is stored here (set values), detector Bias programming
data, firmware to program the PLD's of the 4 DDB's, the Peak value
calculation operation for the detector (see section 2.17 for a discussion of the
Secondary Calibration (QA)).
PRODIGY Service Manual (Rev C - 2000)
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