Scanner Reset - GE Medical Systems PRODIGY Service Manual

The PLD provides a programmable interval timer (PIT) to the CPU. The PLD
prescales it's input clock to generate a PIT base clock of 100KHz. The CPU
writes a 2 byte word to the PIT reload register MSB/LSB. The CPU then raises
the pit_enable bit to start the timer. In response to the rising edge on the
pit_enable, the PIT loads the reload word into it's counting element and
begins counting down. When the count rolls under the PIT asserts /
SAMPLE_INT, reloads the counting element, and begins another count down
sequence. The /SAMPLE_INT line is tied internally to the HE and LE event
counters and causes a synchronous latch of both counting elements. The /
SAMPLE_INT line is also tied to the processor's 2nd external interrupt line, /
INT1. The CPU interrupt handler reads the latched event counters and ships
the data to the host.

2.5.6 SCANNER RESET

The scanner reset register is used to provide failsafe shutdown operation of
the scanner. A falling edge on any of the inputs to this register will latch the
current value of the register and drop the /SCAN_FAIL_ANY output. The MAX
PLD latches the master reset register and raises CPU_RESET in response to
the falling edge on /SCAN_FAIL_ANY. The MAX PLD also provides
SCANNER_RESET as the logical OR of CPU_RESET and!/
SCAN_FAIL_ANY. The FLEX PLD uses it's SCANNER_RESET input as the
enable bit to the tri-state buffers used to drive all safety critical output lines
including shutter control, HVPS relay control, motor relay control, etc. As such
the scanner is locked into a fail-safe mode whenever SCANNER_RESET is
asserted.
The MAX's master reset register will remain latched until the next rising edge
on the HOST_RTS input. When the cSBC is latched into reset by a scanner
error it will remain in CPU reset until the host drops the RTS line and re-
asserts it. It will remain in scanner reset until the CPU reads the scanner reset
register following the next raising edge of the RTS line at which the condition
causing the /SCAN_FAIL_ANY has been cleared. The firmware passes the
value of the reset registers to the host to allowing the host to display
appropriate error messages to the operator. The host will be unable to
perform any scanner related operations until the SCANNER_RESET has
been cleared. Red diagnostic LED's (see 2.5.33) are provided for both
scanner and CPU reset lines. The CPU reset line is tied to the host CTS
output such that the host sees a CTS event when the cSBC enters CPU reset.
The host code provides a CTS event handler which reads the reset registers
and prompts the user accordingly.
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2-52 System Overview
PRODIGY Service Manual (Rev C - 2000)