Ags Roll; Ags Dac - GE Medical Systems PRODIGY Service Manual

2.5.4 AGS ROLL

2.5.5 AGS DAC

HE/LE COUNTERS
PIT MSB/LSB
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PRODIGY Service Manual (Rev C - 2000)
As part of the setup for a move the host and/or firmware must enable the
motors via the /motor_power, trans_enable, and long_enable outputs and
setup the trans_lsw_override, long_lsw_override, /motion_fail_enable, /
motor_fail_enable, and long_motor_fail_axis outputs as desired. If the system
is in scanner reset for any reason the FLEX PLD will over-ride the /
motor_power output and prevent 24V power from reaching the motor drives.
Addressing for the motor control interface is provided below.
This is a read only 8 bit register which returns the count of AGS roll-over
events since the previous read of the register. The AGS roll counter is reset
on read only - it is not tied to the PIT's sample clock.
This port provides R/W access to the AGS circuit's 8 bit U/D counter. The
counter is tied via a dedicated 8 bit bus to the AGS DAC. The DAC's analog
voltage is tied to the gain control input of the variable gain amplifier (VGA)
used to control gain of the detector input signal. As such the firmware can
read this counter to determine the current DAC voltage level and hence gain
level. If ags_enable is low this port gives the firmware direct control of the
AGS DAC as a parallel R/W device. If ags_enable is high, the firmware can
write to the port but the DAC will continue to respond to UP/DOWN requests
from the AGS DCA circuitry and hence quickly return to the AGS current
operating voltage.
These read only ports provide access to the 16 bit event counters which are
incremented each time the DCA circuitry detects an input pulse within the HE
or LE windows (as defined by the LEL, LEH, HEL, and HEH DAC settings).
These counters are read in two 8 bit bus cycles, MSB then LSB. The event
counters themselves consist of a counting element and a bus element. On the
rising edge on the PIT output pulse the counting elements are latched to the
bus element. The PIT output is also tied to CPU external INT 1 and as such
the firmware interrupt handler then has until the next rising PIT edge to read
the counters before the bus elements are latched over with the next sample
count and data is lost.
System Overview 2-51