Prodigy Ii Combined Single Board Controller (Csbc) (Systems Df+12000 And Greater); Csbc System Architecture - GE Medical Systems PRODIGY Service Manual

2.5 PRODIGY II Combined Single Board Controller
(cSBC) (systems DF+12000 and greater)

2.5.1 cSBC System Architecture

cSBC Memory Space
FLASH RAM
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PRODIGY Service Manual (Rev C - 2000)
The cSBC printed wiring board (PWB) is an eight layer rectangular board
measuring 7.400" x 8.100". The PWB is mounted in the via four mounting
holes located 1/4" from each corner and 2 additional interior mounting holes.
The components are primarily surface mount, with board connectors, headers
and a few single-style ICs being the only exceptions.
Four layers were dedicated for routing layers. Sensitive signals were noted
and routed manually and isolated from more powerful signals to reduce signal
interference and crosstalk on the same routing layer. The main power and
ground planes were stacked adjacently on the central inner layers to increase
inter-planar capacitance thus reducing ground bounce and power supply
noise. Traces on the top and bottom layers were kept as short as reasonably
possible and tapped down to an internal trace layer through vias.
Component placement is arranged to separate analog from digital circuitry.
Further isolation was achieved by segmenting the power and ground planes
into analog and digital sections and denying analog/digital plane overlap, thus
preventing digital noise from coupling into the analog section. All scanner
control I/O is run via connectors located on the +24V plane section. The +24V
plane is fully optically isolated from both the analog and digital plane areas to
prevent motor noise from coupling into the analog section, to prevent DC
switching noise from radiating on scanner cables, and to prevent ESD
presented at cable inputs from reaching the digital IC's.
The cSBC employs an Intel 80C251 micro-controller as its processor. This
processor provides 1K of on-board RAM and no on-board ROM. The
controller is clocked at 16 MHz using a crystal.
The cSBC is designed to support a JEDEC-standard, non-volatile FLASH
memory device up to 512K x 8 bits in size for code and fixed data. The board
supports either 128K or 512K SRAM memory device as needed for program
volatile memory. Complete address decoding is provided via the MAX PLD,
the CBSC bus master, allowing the address space to be arbitrary and
changed via the PLD code. The 80251 can address four 64K segments,
referred to as 0x00, 0x01, 0xFE and 0xFF as per Intel literature. The firmware
has the ability to map any FLASH or SRAM segment to any CPU segment via
SFR's in the MAX PLD.
System Overview 2-45