Shutter / Collimator Drive; End Of Exposure Alarm; Panel Led's; Hvps Control - GE Medical Systems PRODIGY Service Manual

2.5.24 Shutter / Collimator Drive

2.5.25 End of Exposure Alarm

2.5.26 Panel LED's

2.5.27 HVPS Control

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2-60 System Overview
The cSBC provide a failsafe mechanism independent of the programmable
logic via the +5V_IO circuit. If one or more of either the E-stop, external E-
stop, or tube thermostat is open, the FET driving the +5V_IO net from the
+5VDC plane will be disabled. The +5V_IO net provides power to the emitter
anode of all opto's which drive critical scanner functions. As such the scanner
will enter a failsafe state in response to these mechanical interlocks, even in
the event of a PLD device failure. The +5V_IO FET will also be disabled by
either a HOST_RTS or CPU_RESET.
The shutter and collimator solenoid drive circuits are the same as that used on
Prodigy I. The FLEX drives an isolation opto which in turn switches a pair of
FET's to control solenoid current. The first FET is used for an initial 'hard hit'
on open commands. It presents 24V directly to the solenoid for several
hundred msec's, resulting in a large initial current pulse to the solenoid. The
second FET provides the 'hold' current through a pair of current limiting power
resistors. The hold FET is tied directly to the /shutter_open_ctrl bit. Note that
the collimator drive is populated only for NT-A and IQ upgrades which use the
old style IQ collimator assembly. The nominal values of the power resistors is
changed between the NT and Prodigy II BOM's to support both the traditional
linear solenoid of IQ, and the rotary solenoid of Prodigy. A jumper or DNP'd
resistor is used to drive the IQ_SHUTTER line to the FLEX such that both
mechanical and optical shutter limit switches are supported.
An on-board end of exposure alarm is provided. The alarm chosen is the
board mount equivalent of that used on Prodigy I.
The 4 panel LED's, power on, X-ray on, source exposed, and laser on, are all
driven PS2501-2 opto's through 750R0 / 1W current limiting resistors.
The HVPS analog control interface is designed to provide maximum
performance at minimum cost. A single, 16 channel multiplexed, 16 bit, high
accuracy, ADC is used in conjunction with several lower cost, lower bit
resolution DAC's. Absolute accuracy of DAC's is poor but errors are calibrated
out by the firmware which monitors the actual DAC output via the ADC. In this
scenario DAC integral non-linearity (INL) specs are not important, sufficient
differential non-linearity (DNL) is all that is required. Serial DAC's and ADC's
are chosen to conserve board space and simplify routing. Serial parts are
typically also lower cost as their maximum bandwidth is limited by the serial
baud rate.
The HVPS AC is enabled via a relay controlled by the cSBC. The line is
primarially used to disable the HVPS by removing the AC to the HVPS via the
relay. AC Power to the HVPS can be left on for up to one hour after
generation of x-rays to prevent AC cycling between concurrent scans.
PRODIGY Service Manual (Rev C - 2000)