Interrupts; Master Reset - GE Medical Systems PRODIGY Service Manual

2.5.14 Interrupts

Bit Name
0 HOST_UART_INT
1 DEBUG_UART_INT
2 DMB_UART_INT
3 HVPS_ERROR_INT
4 8mS_CLOCK
5 POWER_FAIL_INT
6 Unused
7 Unused

2.5.15 MASTER RESET

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2-56 System Overview
The CPU's interrupt capacity is effectively increased by running several
interrupt signals to a register in the MAX PLD and tying the register output to
the CPU external INT 0 input. The firmware interrupt handler for INT 0 then
reads this register to identify the source of the interrupt and handles it
accordingly. The firmware then writes a bit masked '1' back to the IIR to clear
the bit of the interrupt it has serviced (the R/C in the table stands for READ/
CLEAR).
R/ Def. Description
W
R/C N/A Host UART interrupt.
R/C N/A Debug UART interrupt.
R/C N/A DMB UART interrupt.
R/C N/A HVPS error interrupt.
R/C N/A 8ms clock tick interrupt from FLEX PLD.
R/C N/A Power down pending in 5ms interrupt from DC supply.
N/A N/A Expansion room.
N/A N/A Expansion room.
The master reset register will force a CPU and scanner reset condition on the
falling edge of any of its listed inputs. The contents of the register will be
latched at the time of reset such that when the CPU next comes out of reset
the firmware can read the register to determine what caused the preceding
reset and report the appropriate code to the host. If the reset was cause by
the CPU_RST_WR input, the suicide reset register contains the specific error
code. If the reset was cause by the /SCAN_FAIL_ANY input, the scanner
reset register contains the specific error code.
The CPU and scanner resets will remain latched until the next rising edge of
the RTS input. At this time the CPU reset will be cleared if /POWER_RESET
bit is not asserted and the scanner reset will be cleared if /SCAN_FAIL_ANY
is high.
PRODIGY Service Manual (Rev C - 2000)