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MAINTENANCE
Table 7-16. A/D Module
Digital Circuitry
Checks
SteF
-
1
ItemiComponent ___
Programming
2
LJ369, pin 7
3
U369, pin 9
4
U369, pin 14
5
U369, pin 12
6
U369, pin 5
7
Front panel
8
U369, pin 16
9
U369, pin 18
10
U369, pin 20
11
12
13
Front panel
U352, pins 3, 4, 7, 8, '13,
14, 17, 18
lJ360, pins 3, 4, 7, 8, 13,
14, 17, 18
14
U306, pins 1 and 8
15
U310, pins 1 and 8
16
U347, pins 1 and 8
17
U356, pins 1 and 8
18
U322, U342, U351, U359,
pin 8
19
U322, U351, pins 1 and 2
20
U342, U359, pins 1 and 2
21
U351, U322, pins 3-6,10-U
22
U342, LJ359, pins 3.6,10-13
23
U307, U308, U309, pin 2
24
U345, pin 4
25
U346, pin 4
26
U312, pin 1
27
U312, U334, pins 3-6, 9-13
28
29
30
31
32
33
34
-
U303, pins 11-18
U304, pins 2-9
U317W320, U337W340,
pin 4
U317-U320, U337W340,
pin 15
U316, pin 1
U315, pin 25
U301, U302, pins 3 and 4
,
i.
i
Required Condition
Remarks
Program 10,000 samples, 10~s~
interval, continuous
trigger mode.
All voltages referenced to A/D
digital common (TRIGGER
jack
outer shell).
Data pulse burst ewry IOrsec.
Data pulse burst every lO,,sec.
2pec negative going pulse every 10qx
iMHz
square wave.
TOOnsec negative going pulse
rvery lO,ea
during
measurement.
Program 100 samples.
Positive going pulse when range
outton is pressed.
Pulse burst when range button is
pressed.
Pulse burst when range button is
pressed.
Program 10,000 samples.
A/D data at sampling
rate.
Odd bit data
Even bit data.
Data shift cnablc.
Data shift clock.
AID trigger pulse.
Serial control strobe.
High byte dat'l
A/D data at sampling
rate.
Low byte data.
Pulse train when range button
is pressed.
Pulse train when range button
is pressed.
Pulse train when range button
is pressed.
Pulse train when range button
is pressed.
5MHz square wave.
Data shift clock.
Serial pulse train during
measurement.
Serial pulse train during
measurement.
A/D data pulses.
A/D data pulses.
10MHz square wave.
2~s~ negative pulse every 1Ofiscc.
2qec negative pulse every 2msec.
200nsec positive pulse every 10fisec.
Address counter pulses, various
duration.
Check for stuck bit on data bus.
Check for stuck bit on data bus.
200nsec negative pulse every 8~s~
when not measuring.
2001~~ negative pulse every 60rsec
when not measuring.
30MHz square wave.
lMHz
square wave.
Brief data pulse train upon power up.
Odd bit serial AlI) data.
Even bit serial A/D data.
Odd bits of parallel data.
Even bits of parallel dat,l.
Sample counter clock.
Trigger c<,untcr count pulse.
Second stage count pulse.
Address counter count pulse.
Count depends on programmed
number of samples.
Data bus DO-D7
Data bus DO-D7
RAM RAS during
MI'U memory
access.
RAM CAS during
MI'U memory
XCeSS.
DMA controller
clock.
2 system clock.
NVRAM
data.
7-37
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