Memory Map - Keithley 194 Instruction Manual

PRINCIPLES OF OPERATION
6.6.4 Address Decoder
Several ICs are used to decode the memory map into
segments and blocks. A general memory map for the in-
strument is shown in Figure 6-7. A more detailed summary
of the map is listed in Table 6-2.
Table 6-2. Memory Mapping
Address* Description
IC(s)
$OEOOO-$OFFFF RAM u102
$10020
Keyboard VIA u410
510082
Display PIA u404
$10084 Display PIA u407
$10100 IEEE-488 Interface U127
510200 Analog Output U412-U415
$20000-52FFFF
Channel 1 RAM U317W320,
u337-u340
$30010
Channel 1 A/D VIA U323
$30040 Channel 1 A/D PIA u315
540000-54FFFF Channel 2 RAM U3PLJ320,
u337-u340
550010 Channel 2 A/D VIA U323
550040 Channel 2 A/D PIA u315
560000-$7EOOO ROM u103-u105
U108 is used to divide the MPU address range into 64K
byte segments. This IC is a l-of-8 decoderidemultiplexer
(74LS138). The IC inputs (A,B,C, and GZA) monitor the
A16-A19 address lines, and the outputs drive the select cir-
cuits for the various peripheral and memory segments. The
corresponding output will go low when a particular 64K
segment is selected. For example, YO will go low when
selecting the ROM memory block, which lies in the range
of 500000 to $OFFFF.
The ROM memory segment is divided into blocks. ROM
decoding is performed by UWA, one half of a dual l-of-4
decoder (74LSl.39). The other half of UlW, is used to decode
the IEEE-488 interface and I/O board circuits.
Figure 6-7. Memory Map
6.6.5 Control Circuits
Several miscellaneous circuits are used to gcncratc COIJ-
trol signals for the MPU bus. Thcsc include LJllO, Ul20,
and a section made up of U113A. LJ114, and U126A.
UllO is an S-bit serial-to-parallel converter (74LS165) that
is used to generate the DTACK (Data Transfer
Acknowledge) signal for the microprocessor. U120 is also
a 74LS165 IC being used to generate the BERR (Bus Error)
signal for the MI'U. Each of these ICs functions has a delay
line to provide a specific delay period for the correspond-
6-17