Digital Circuitry; Microcomputer; Address Decoding; Pia - Keithley 485 Instruction Manual

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4.4 DIGITAL
CIRCUITRY
Model 485 operation is controlled by the internal microcom-
puter.
This section briefly describes the operation
of the
various sections of the microcomputer
and associated digital
circuitry.
For complete
circuit
details refer to schematic
diagram number 485108
at the end of this manual.
4.4.1 Microcomputer
The microcomputer
(MPU) centers around the 146805E2
CMOS microprocessor.
It is an 8 bit microprocessor
with
direct addressing of up to 8k bVtes on a shared address and
data bus.
Timing of the microprocessor
is accomplished
by the use of
YIOI;
a 32788MHz
crystal. Internally this frequency
is di-
vided down bY 5 to obtain a bus operting
frequency
of
855.38kHz. This is present on the address strobe of U120 (pin
8) and supplies timing to all other parts of the instrument
through the binary divider U116.
The software for the MPU is stored in U113 (PROM). Tem-
porary storage is provided by Ul12. U112 is used to store the
calibration
constants
on power
up and as RAM for the
microprocessor's
in-house functions.
It also stores readings
for the data logger. U123 is the NVRAM and is used to store
the calibration
constants
which
are moved to the RAM
KJ112) on power up.
4.4.2 Address Decoding
Ullg
is used to latch in the address that is on the bus when
the address strobe of VI20 goes high and presents it to the
PROM full31
during data strobe.
4.4.3 PIA
Ulll
provides for most of the control of the instrument.
It
controls all ranging hardware, AID converter, and data out-
put and input for the IEEE option.
4.4.4 Display Board
The LCD display is driven by a flat pack LCD controller chip
U201 and it communicates
to the microprocessor
through
four control lines. During power-up the microprocessor con-
figures U201 to drive the triplexed display.
In order to drive the display correctly four voltages are ob-
tained from R121. The clock required bY U201 is obtained
from U118.
The display board also houses the special function
keys:
LOG, REL, STO/CLR and RCL.
4.5 DIGITAL
CALIBRATION
The Model 485 uses digital calibration to eliminate calibration
potentiometers
in the instrument.
The constants
that the
Model
485 uses are stored
in a nonvolatile
electrically
alterable read only memory fU1231, and are read on power-up
of the instrument.
There is one constant for each range.
4.6 POWER SUPPLY
Fuse FlOl is the LINE FUSE which is internally accessible.
SlOl is the power ON/OFF switch, and S102 selects 115V or
230V operations bY placing the transformer primary windings
in parallel or series.
TlOl,
the power transformer
has two secondary windings;
one for the Model 485 and the other for the IEEE option
(Model 4853). The bridge rectifier (CRIOI) functions
as a
fullwave rectifier for both the plus and minus supplies. RI25
limits current to the 12V zener fVR106) and to the batteries (if
installed) for charging. The zener acts as a pre-regular to the
+ 5V regulator.
4.7 MODEL 1758 BAlTERY
OPTION
Maximum battery charging rate is acieved when the instru-
ment is connected to line power and the ON/OFF switch is
off. Fullwave rectified voltage from CR101 is applied to RI02
and BTlOl
to charge the batteries. 0101 acts as a current
sink if the charging current rises above 150mA. The batteries
are of the quick recharge o/pe and will charge in 8 to 10
hours. With the instrument turned on the batteries will trickle
charge at approximately
40mA.
With
the battery
peck installed,
the negative
supply
is
generated using a CMOS voltage inverter (U1011. The output
of the inverter is applied to CR101 and Cl01 for filtering.
Low battery detection
is accomplished
by the comparator
fU102) and the microprocessor.
A voltage
level of 8.8V
across ET101 signals the end of useful battery life. The trip
level for the comparator is set by R103 and R104.
4-4

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