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PRINCIPLES OF OPERATION
6.6.2 68008 Microprocessor
The 68008 microprocessor
(UlOl) is almost identical
in
operation
to its full 16-bit brother--the
68000. While the
68000 has a 16.bit data bus, the 68008 has a data bus that
is only eight bits wide. One other difference
lies in the
memory addressing capabilities.
The 68008 is capable of
addressing
1 megabytes, while the 68000 can address 16
megabytes.
Internally,
the 68008 has eight 32.bit data registers and
seven 32.bit
address registers.
In addition
two stack
pointers--a user stack pointer and a supervisor, or machine
stack pointer--are included to enhance operation. Because
of the many internal
32-bit operations
that can be per-
formed, many Model 194 functions are handled faster and
more efficiently
than would be possible with a standard
B-bit processor.
As shown on the diagram (page 2 of drawing
number
194-106), the 68008 has eight data lines (DO-D7) and 20 ad-
dress lines (AO-A19). Numerous
control lines supervise
data transfer
between
the device
and memory
and
peripheral
ICs as follows:
AS: set low when a valid address appears on the address
lines.
DS: set low when valid data is available on the data lines.
R/W: Set high when reading
data from memory
or a
peripheral
device; set low when writing
to memory or a
peripheral
device.
Interrupt Control (IPLl/IPL2):
These interrupt control lines
indicate the coded priority
level of the device that may be
requesting
an interrupt.
Data Transfer Acknowledge
(mACK):
This input line in-
dicates that a data transfer has been completed
when it
is set low.
Processor Status (FCO, FCl, FCZ): These three lines indicate
the status of the processor. In the Model 194, these are
decoded by U126B to acknowledge
an interrupt.
Enable(E): This line provides an enable clock to peripheral
ICs such as the I'IAs and VIAs present in other sections
of the instrument.
CLK: The 1OMHz microprocessor
clock is applied to this
input.
Valid Peripheral Address (VPA): This input terminal pro-
vides
synchronization
of data transfer
when
com-
municating
with peripheral
10.
RESET and HALT: A low logic level is applied to these ter-
minals during
power up in order to reset the processor
and peripheral
ICs.
Bus Error (BERR): A low logic level on this input terminal
indicates
to the processor that a bus error such as a
nonresponding
device has occurred.
V, and GND: The +5V digital supply provides power to
the IC through
these terminals.
6.6.3 Clock and Reset Circuits
The clock that drives the microprocessor originates in YlOl
as a 20MHz stable reference signal. This clock signal is
divided
down to 10MHr by U112A, which is one-half of
a dual JK flip-flop
(74LS73). The 1OMHz signal is then ap-
plied to the CLK input of the 68008 microprocessor.
The
clock signal is then divided
in half once again by U112B,
and the resulting
5MHz clock signal is then sent to the
IEEE-488 GI'IA (General Purpose Interface Adapter) IC,
U127
The 1OMHz clock is also normally used to drive some A/D
control circuits. However, a clock pulse, applied to the rear
panel external clock input, can be used to synchronize
a
number of Model 194s together. U123, UlllC,
and U122A
function
together to detect and gate the external clock in-
put. If a suitable signal is detected, the external signal is
then routed to the digital control circuits instead of the
usual 10MHz MPU clock.
Upon power up, the MPU is reset by briefly placing the
RESET and HALT terminals at a low logic level. This reset
action is performed
by a timing circuit made up of UlO6
(8211) and associated components.
The reset pulse is also
applied to numerous
peripheral
ICs located on the AID
converter module(s),
and the I/O board.
6-16
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