Keithley 194 Instruction Manual page 162

PRINCIPLES OF OPERATION
Serial-to-Parallel Data Conversion
Parallel A/D converter data is converted into serial form
by two shift registers and transmitted across two opto-
isolators, as described previously. Data is then converted
back to parallel by two sets of serial-to-parallel converters.
One set supplies data to the trigger comparator and real
time output circuits, while the other serial-to-parallel con-
verters feed data to the 64K dual-port memory.
Digital Trigger
The digital trigger circuits consist of a 16-bit digital com-
parator and a 16.bit latch. The latch is loaded serially with
two control bytes from the microprocessor. As discussed
earlier, this control information is part of the lo-byte con-
trol word that is passed serially as part of the control
SlXJ"eW2.
The digital comparator monitors both the preset trigger
level data in the 16-bit latch, and data from the A/D con-
verter. If the two binary numbers are the same, a trigger
pulse appears at the output of the comparator. If the in-
strument is programmed to trigger from the input signal,
the RUN/STOP flip-flop is triggered to start a series of A/D
readings. The number of readings to be taken will depend
on the reading counter.
Sample Counter
The sample counter is made up of an X-bit latch and a
presettable counter. The latch is serially preloaded with
control information from the microprocessor via the SO-bit
control word. Once the &bit latch contains the correct in-
formation, the downcounter is loaded with the count in-
formation. The counter then decrements by one count each
time an A/D sample is taken. The count pulse is fed across
the opto-isolator from circuitry located in the A/D section.
Trigger Period Control
A similar counter arrangement is used to control the trig-
ger period. A l2-bit latch is loaded with data from the serial
control word. The value loaded will depend on the pro-
grammed sampling interval. Once the latch is loaded, the
counter is preset from the latch by a control pulse. The
countdown period is controlled by the 1OMHz clock of the
microprocessor, or by an external clock pulse if one is
applied.
Since the counter is only 12 bits wide, it counts only to
4096. With the 1OMHz clock, the maximum count period
is: 4096110MHz = 0.4096msec. Thus, to extend the trigger
period to the one second maximum, a separate software
counter must be employed as well. Every time the hard-
ware counter reaches zero, a microprocessor interrupt is
generated, at which point it increments the software
counter. Once the correct conditions for both the software
and hardware counters are reached, an AID trigger pulse
is generated, and another reading sample is taken, assum
ing that the RUN/STOP and TRIGGER ENABLE signals
are at the correct logic level.
64K Byte Dual-Port Memory
The 64K byte dynamic memory is shared by the AiD con-
verter and the mircroprocessor--an arrangement that gives
the memory block its dual-port name. To allow both cir-
cuits access to the memory, a number of memory control
and multiplexer circuits are necessary. The dynamic
memory controller refreshes the dynamic memory and
also multiplexes the addresses. If the 68008 IMI'U is xcess-
ing memory, the address comes from its address bus. If
A/D data is being stored, the address is supplied by the
address counter.
In a similar manner, the microprocessor and AID data
busses are multiplexed into the memory data lines. When
the A/D is storing data, it gains access to the data lines
of the memory ICs, while the MPU gains XCI'SS tu the data
lines when it requires data access.
Real Time Output
One final portion of the digital control circuitry is the redI
time output, which provides data output for other equip-
ment at the conversion rate. Two R-bit latches store essem
tially the same data bits that xc stored in memory. Real
time output data transmission is controlled by additional
logic circuitry not shown on the block diagram.
6.5.2 Isolator Data Transmission
For the following discussion, please refer to drawing
number 194-126, page 2 located at the end of Section 8.
6-H