Keithley 194 Instruction Manual page 169

PRINCIPLES OF OPERATION
ing signal. DTACK is used to tell the processor that data
transfer has been successfully completed, while BERR in-
forms the processor that there is a problem with the cycle
currently being completed. Typically, such an error will
occur when a device on the bus does not respond as
intended.
The VMA and VPA signals are generated by U114 with the
help of gating from Ull3A and U126A. U114 is a dual JK
flip-flop (74LS73), while Ull3A and U126A are standard
gates. The VMA signal is used to signal to peripheral
devices that a valid address is present on the address lines.
VI'A is an input line that informs the processor that the
address now in effect is a peripheral address, and the E
line should be used for data transfer.
6.6.6 Memory Circuits
Software for the 68008 microprocessor is contained within
ROM ICs. The ROM (Read Only Memory) ICs in the
Model 194 include U103, U104, and U105. U102 provides
working storage for the MPU.
6.6.7 Buffers
Throughout the Model 194, numerous ICs in the
microcomputer, A/D module(s), I/O section, and scanner
(if present) are connected to the address, data, and con-
trol buses. Because of the large number of circuits involved,
each bus must be given additional drive capability--a task
performed by several buffer ICs.
Address bus buffering is done by U115 and U116, each of
which is an octal buffer (74LS244). Since address bus in-
formation flows only in one direction (from the MPU to
external circuits), these ICs are uni-directional.
In a similar manner, U109 and U118 are used to buffer
various control lines. Some control signals flow from the
microprocessor to external circuits, while others flow from
external components to the MPU.
Since information on the data bus flows in both directions,
a bidirectional buffer IC must be used. UT17 is an octal
transceiver IC (74LS645) that provides such capabilities.
The direction is controlled by thelogic level on the DIR
line, which is connected to the R/W signal. When DIR is
high, data flows from external circuits, through Ull7, to
the MPU, as the microprocessor is performing a read
operation under these circumstances. When DIR is low,
data flows from the MPU to external ICs due to the write
operation involved.
6.6.6 IEEE-488 Interfacing
The IEEE-488 interface is made up of Ul24, U125, and U17.7
U127 is a GI'IA (General Purpose Interface Adapter), 9914,
while U124 and U125 are 75160 and 75161 interface bus
drivers.
The 9914 GPIA simplifies interfacing to the IEEE-488 bus
because many control sequences take place automatical-
ly. For example, when a data write to the bus is performed,
the handshake is automatically performed by the 9914.
On the MI'U side, data transmission is performed much
like any other data bus transaction. MPU data access is
performed through the DO-D7 lines, while the RSO-RS2
lines serve to select among the 14 internal registers (seven
read, seven write) of the 1C. Chip selection is performed
by the CS line.
The output of the 9914 IC is in standard IEEE-488 format:
the eight data lines (DIOl-DIOR), the three handshake
lines (DAV, NRFD, and NDAC), and the five management
lines (ATN, REN, IFC, SRQ, and EOI) are all active low
with approximately zero volts representing a logic one.
The two bus drivers (Ul24 and UlZ5) are neccssaly to bring
the drive capability of the interface up to the requirements
of the IEEE-488 standard, which includes provisions for
a maximum of 15 devices. The outputs of the bus drivers
are connected to J1004, which is a standard IEEE-488
connector.
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