Keithley 194 Instruction Manual page 159

PRINCIPLES OF OPERATION
6.4.3 Parallel-to-Serial Data Conversion
The parallel data output of the A/D converter must be con-
verted into serial form before it can be transmitted over
the opto-isolators to the digital control circuitry. This task
is performed by LJ376 and U385, which are parallel-to-serial
converter ICs (74LS165). As pointed out earlier, a dual-serial
transmission scheme is used, with odd/even bit pairs
transmitted simultaneously. Thus, U376 converts and
transmits odd data bits (Dl, D3 and so on), while U385
handles the even data bits (DZ, D4, etc.).
At the end of a converter cycle, a signal derived from the
A/D converter EOC signal is used to pull the PL terminals
on U376 and U384 low. This action latches the A/D con-
verter data into these two ICs. Data is then shifted out the
Ql terminals under control of a clock pulse applied to the
Cl'1 terminals of the two 1Cs. The data bits arc first buf-
fered by sections of U37l (74LS244) before being applied
to the LED sections of the data transmission opto-isolators.
U367A transmits odd data bits, and U367B transmits even
data bits. 'The receiving ends of these isolators convert the
generated light pulses back into electrical impulses in the
usual manner. 'The serial pulses are then converted back
into parallel to be stored in memory, used by the trigger
circuits, and transmitted out the real time output. These
aspects are discussed later in this section.
6.4.4 Data Transmission Control
The data transmission process is controlled by a stable
reference clock and several other components. These in-
clude YIOI, U383A, U374, U375, U383C, U384, U371E and
U37IF, and U366B and U3668.
YlOl generates a stable 10MHz reference signal for the data
transmission process. This signal is squared by U383A, one
segment of a quad 2.input NAND gate IC (74LSOO), and
then applied to section 1 of a dual D-type flip-flop, U374
(74LS74). This flip-flop divides the signal by two to form
the 5MHz clock that synchronizes data transmission. The
second section of U374 and the first section of U375 (also
a 74LS74), make up a shift register that effectively delays
the A/D converter EOC signal by two cycles. Meanwhile,
U383C is used to gate the EOC signal, while U384, a
parallel-to-serial converter (74l.S165), is used to select 8.
or 76.bit data transmission modes.
As previously described, the A/D converter EOC line goes
high when data is ready at the A/D converter data lines.
'This logic level is then latched into the 2Q output of U374
with the next 5MHz clock pulse and applied to the 1D in-
put of U375. After two clock pulses, both inputs of U383C
will be high, and its output will go low. This action causes
6-8
AID converter data to be latched into U376 and U384. At
the same time, the logic levels on the PO-P7 terminals of
U384 will be latched into its register. If the converter is be-
ing operated in the R-bit mode, Pl-I'4 will be high; however,
these four inputs will be low if the converter is operated
in the 16.bit mode.
As each SMHz clock pulse occurs, an odd/even pair of A/D
data bits is shifted out U376 and U384. At the same time,
bits previously latched into U384 by the delayed EOC
signal will be shifted out. Thus, the bits latched into U384
will be shifted out through U37lF and U366B to the digital
control circuitry. After four clock cycles (S-bit mode) or
eight clock cycles (16.bit mode), the serial output of U384
will go high, causing the transmitted data to be latched
into registers located in the digital section, as discussed
below. In this manner, U384 controls whether I(-bits or
16.bits arc transmitted.
The SMHz clock is used to synchronize the operation of
the parallel-serial convertors, U376, U384, and U385, as
discussed previously. In addition, this clock is used to syn-
chronize circuits in the digital section. Towards that end,
the 5MHz clock is transmitted through U37lE and opto-
isolator U366A to the digital circuits discussed later in this
section.
The A/D converter module must be triggered before it will
perform a conversion. 'lkigger pulses orginate in the trig-
gcr control section of the digital circuitry discussed below.
These trigger pulses arc transmitted through U365 and buf-
fered by U37IC, after which they are applied to the A/D
converter.
6.4.5 Serial Control
Various operating aspects of the A/D converter and input
amplifier are controlled by bits in the serial control word.
The serial control word is made up of 10 bytes (80 bits),
five of which control the A/D converter or the input
amplifier. These five bytes are shifted into serial shift
register ICs, U379, U380, U361, U370, and U382 (4094). 'The
remaining five bytes are shifted into similar ICs which are
located in the digital section to be discussed later.
Serial control word data is generated in the digital section,
shifted in through U364, and applied to the DATA input
of U379. The clock necessary for the shifting process is ap-
plied through U364, buffered by U3?IA, and applied to
the CLOCK input of U379. After eight bits have been
shifted in, data overflows out the Q.? output of U379 to the
DATA input of U361. In a similar manner, the Qs outputs
of the remaining shift register ICs (U370, U382, and U380)