Keithley 194 Instruction Manual page 9

4.9.20
Save (L) ......................................................
4.9.21 Recall(A)
.....................................................
4.9.22 Hit Button (II) .............. ............ ....................
4.9.23
Display (D) ...................................................
4.9.24
Self Test(J) ...................................................
4.10
TRANSLATOR MODE ............................ ...... ......
4.10.1
Defining Translator Words (ALIAS) .............................
4.10.2 Enabling and Disabling the Translator Mode (KNEW and OLD)
4.10.3
Combining Translator Words ............................
......
4.10.4
Reading Back Translator Words (LIST). ..........................
4.10.5
Purging Translator Words (FORGET) ............................
4.11
BUS DATA TRANSMISSIOX TIMES.
.............................
SECTION 5-PERFORMANCE VERIFICATION
,...,
......
......
......
......
......
......
......
......
......
......
......
......
.,....
4-46
4-47
4-47
4-48
4-49
4-50
4-50
4-52
4-53
4-53
4-54
4-54
3.1
1NTRODUCTION
.............................................................................
5-l
5.2
ENVIRONMENTALCONDITIONS ............................................................. 5-l
5.3
5.4
5.5
5.6
5.7
5.71
5.72
5.8
INITIAL CONDITIONS
RECOMMENDED TEST EQUIPMENT .................
TEST EQUIPMENT CO1 'JNECTIONS ...................
VERIFICATION PROCEDI JR1
COMPUTERIZED VERIFICATION ......................
HP-85 Verification Program
IBh? PC/Model 8573 Verification Program
AC FREQUENCY RESPONSE
SECTION 6-PRINCIPLES OF OPERATION
6.1
6.2
6.3
6.3.1
6.3.2
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.5
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
6.5.7
6.5.8
6.5.9
6.6
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.6.6
6.6.7
6.6.8
... 5-l
....................................... 5-l
....................................... 5-2
....................................... 5-2
....................................... 5-3
....................................... 5-3
....................................... 5-5
....................................... 5-6
INTRODUCTION .............................................................................
6-l
FUNCTIONALDESCRIPTION
.................................................................
6-l
ANAU)GCIRCU~RY ......................................................................... 6-3
BlockDiagram .............................................................................. 6-3
Circuit Description .......................................................................... 6-3
A!D CONVERTER ............................................................................ 6-4
Converter Block Diagram .................................................................... 6-4
C onverter MDdule ........................................................................... 6-6
FaraIlel-to-Serial
Data Conversion ............................................................. 6-8
Data Transmission Control ................................................................... 6-8
Serial Control ............................................................................... 6-8
DIGITAL CONTROL CIRCUITRY. .............................................................. 6-9
Block Diagram of Digital Circ~uitry ...................................................... ..... 6-9
Isolator Data Transmission, ................. ................................................ 6-11
Serial-to-Parallel Data Conversion ... ..............................
Sample
Counter ..................................................
Digital Trigger Comparator Circuits. ................................
Trigger Period Control Logic .......................................
64K Byte Dual-Port Memory .......................................
Digital Control-to-Microprocessor Interfacing Circuits ................
Non-Volatile Memory Circuits (NVRAM) ............................
MlCROCOMI'UTER ................................................
Microcomputer Block Diagram .....................................
68008 Microprocessor .............................................
Clock and Reset Circuits ..........................................
Address
Decoder .................................................
Control Circuits .......................... .......................
Memory Circuits ..................................................
Buffers ..........................................................
IEEE-488 Interfacing ...............................................
.... ...................
........................
6-12
6-12
6-12
6-13
6-13
6-14
6-N
6-14
6-14
6-16
6-16
6-17
6-U
h-18
6.la
6-E
iv