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PRINCIPLES
OF OPERATION
are connected serially, with the Qs output of the preceding
IC being connected to the DATA input of the following
IC.
Once all 80 bits (40 in the A/D section) are shifted in, the
strobe pulse is applied to latch the various bits into the
shift register outputs. In the A/D section, this strobe pulse
is applied through U365, buffered by U37lD, and applied
to the STROBE terminals of the five shift register ICs. Since
all STROBE terminals
are connected together, all 80 bits
are latched simultaneously.
The five shift registers ICs in the A/D converter section
perform the following
control functions:
1. The Qa output of U379 is used to select 8. or &bit
upera-
tion of the A/D converter. If Qa is high, the AID con-
verter operates in the a-bit mode; if Q. is low, the con-
verter operates in the lh-bit
mode. Q1, Q,, and Qs
through Q, of U379 arc used to control FETs in the in-
put amplifier
section. Elements of LJ377 and U378 are
used to convert standard logic levels into +15V levels
to turn the FETs on or off.
2. The Qe through Qe outputs of U380 arc used to control
relays K301, K302, and K303 in the input amplifier. U381
supplies the drive capability
to power the relay coils.
3. U361, U370, and U383 are used to store digital calibra-
tion information
for the A/D converter. This informa-
tion is converted to analog form by two 12.bit DACs
(LJ362 and U363), as previously discussed. U361 and four
bits of U370 are used for AID reference adjustment,
while the remaining
four bits of U370 and roll eight bits
of U382 are used to store converter offset data
6.5 DIGITAL CONTROL
CIRCUITRY
The digital control circuitry
within
the Model ~194 is used
to store data and control its flop,, control Ail) triggering,
and keep track of the number of s;tmples taken with its
sample counter. The following
paragraphs
dcscribr
the
operation of the digital circuitry in detail. First an wc'r\~i~~\
is presented
in block diagram
form
.Next a detailed
analysis for each of the major sections is given. These
descriptions
are keyed to various
schem.ltic
diagr.~nl~
located at the end of Section 8. 'The pertinent
schcnutic
or schematics
are called
out
with
each individu'll
description.
6.5.1 Block Diagram
of Digital
Circuitry
A simplified
block diagram is shwvn in IFigure h-.5 .\l.lj<,r
circuitry includes that necessary to c~mw~t sc'&~l A Lo) <'ow
verter data into parallel furm, trigger cumpar.xtor, trik<et~
control
logic, sample counter,
the 64K byte dual-port
memory, and the real time output. Fc)r claritv, some of the,
circuitry located in the A/D converter scction'is '~1~ shown
on the diagram.
6-9
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