Digital Circuitry; Memory Elements; Device Selection - Keithley 595 Instruction Manual

THEORY OF OPERATION
The integrator is made up of Ul32 and Cl32 When&e in-
put to the integrator is applied, the integrator
output ramps
up until its voltage is slightly higher than the &age to the
inwriing input of the charge balance comparator (Ul37B).
When the
43
output of the clock generator (UlZ5) goes
high, the output of Ul%A is low, and the Ql output of
Ul2a wiu go high. This action injects the charge balance
current into the integrator input. Since the charge balance
current is much larger than the sum of the input and level
shift currents, the integrator output now ramps in the
negative direction. The integrator output will continue to
ramp in the negative direction until the output of Ul36B
goes low. Note that the 42, Q3 and Q4 outputs of Ul25
must all be high for the output of Ul36B to go low.
The output of Ul35A is gated with the Ql output of the
clock generator (Ul25) by Ul36C. Each time Ql goes~high
while the Ul35A output is high, a pulse is fed to the
microprocessor. The MFU then counts the total number of
pulses that~occur during the charge balance phase.
The charge balance phase lasts for one line cycle (16.67 or
20.0msec). At the end of this period, the output of the in-
tegrator is resting at some posititi voltage. Since the in-
tegrator output is connected to the non-inverting input of
the single-slope~comparator (U137A), the single-slope com-
parator output remains high until the integrator output
becomes negative.
During the single-slope phase, QllO is turned off to d&con-
nect the ii@ut and charge balance currentsfrom the in-
tegrator input. In place of these two currents;~ the single-
slope current s injected into the integrator input causing
the output to ramp in the negative direction. This current
is developed by connecting one end of Rl53 to +5V through
Ul35C. As long as the integrator output remains positive,
the Ql pulses from UlZ5 are transmitted to the micro-
processor, where they are counted to be used in the final
reading. Once the single-slope comparator output goes
negative, the Ql pulses are turned off by Ul36C.
7.10 DIGITAL CIRCUITRY
Model 595~ operation is controlled by the internal microcom-
puter and associated software. The following paragraphs
briefly describe the various aspects of the digital circuitry.
Descriptions are keyed to the digital circuitry sche&ic
(drawing number
595406,
page 2) located at the end of Sec-~
tion
9.
7.10.1 Microcomputer
Microcomputer operation centers around the 8 bit 146805
CMOS microprocessor, UlW. The device utilizes an 8 bit
data bus and incorporates a multiplexed data/address bus
for the lower eight bits of the 12 bit address bus. The 146805
has 112 bytes of on-chip memory, two 8 bit I/O parts, and
is capable of directly addressing 8K bytes of memory. The
microprocessor unit has direct con&o1 over the display, front
panel switches, analog-to-digital converter, the voltage
source, the DEE-488 bus, as well as the Meter Complete
output and the Fxternal Trigger Input.
Microprocessor timing is performed by YlOl, a 3.2768 MHZ
aystal. The signal is internally divided by five to obtain a
bus operating frequency of 655.36kH.z. This signal is pre-
sent at the A5 terminal of the processor, and is used as a
control signal to strobe the lower ordered eight bits of the
address into the address latch, U108. A 655.36Wz signal
is also present at the DS terminal to act as a system clock.
7.10.2 Memory Elements
Software for the Model 595 is stored in Ul.06, a 27128 16K
X 8 PROM. Temporary storage is afforded by Ulorl, a 6116
2K X 8 RAM IC. The microprocessor unit uses the RAM(
for temporary storage.
Calibration constants, the display mode, and the IEEE-488
primary address are stored in the NVRAhJ, U104. During
the power-up cycle, NVRAM data is transferred to normal
RAM to allow easier access during operation. While data
transmission to the ROM and RAM are done in parallel,
NVlWM data transmission is performed serially.
7.103 Device Selection
The
146805
processor can directly address only 8K bytes
of memory. The Model 595 requires greater addressing
capability, as l6K of ROM, 2K of RAM, and other memory
space requirements are present in the system. To get around
this problem, device selection circuitry is incorporated with
the micorcomputer.
Device selection is performed by elements of Ulll, Ull2,
Uli6 &d LJW. Microprocessor unit lines used, part of the
selection process, include the A%Al.2 address lines, the
7-18