Keithley 194 Instruction Manual page 163

PRINCIPLES OF OPERATION
The 5MHz shift clock and opto latch signals are applied
through opto-isolators located in U366. As with the A/D
converter data signals, these logic levels are buffered by
sections of U369 before being applied to other circuits.
Several logic signals originating in the digital control sec-
tion are passed through the isolators to control the A/D
converter and input amplifier. These signals include the
serial data, clock, and strobe signals for the analog con-
trol bits, and the A/D trigger pulse. These signals are
transmitted to the A/D converter section by opt"-isolators
U364 and U365. As with the remaining signals, these levels
are first buffered by elements of U369.
6.5.3 Serial-to-Parallel Data Conversion
Circuits for the following discussion will be found on
schematic drawing number 194.126, page 3 located at the
end of Section 8.
Serial-to-parallel data conversion is performed by two sets
of circuits. One set converts data for the digital trigger cir-
cuits, while the other performs the conversion for the
memory and real time output circuits. Even-bit A/D con-
verter data is applied to the A and B inputs of U342 and
U359, while odd-bit converter data is applied to the A and
B inputs of U322 and U351. U322 and U342 convert serial
data to parallel for the memory, and U351 and U359 per-
form the same conversion process for the digital trigger
and real time output circuits. Each of these four ICs is a
serial-in, parallel-out shift register (74LS164). The data shift-
in process is controlled by the 5MHz clock that originates
in the AID converter section.
The 16.bit parallel output of U351 and U359 is applied to
the digital comparator and real time output circuits dis-
cussed below. The 16.bit parallel output of U322 is latched
into U321 and U341, which are used to store the A/D con-
verter data briefly before it is stored in memory. U321 and
U341 are octal D-type flip-flops (74LS374), which are
equipped with 3-state outputs. Once data is latched into
these two ICs, the outputs are turned on by placing the
CONT terminals low, thus feeding data to the data lines
of the memory ICs.
6.5.4 Sample Counter
The sample counter circuits are located on drawing number
194.126, page 3.
The sample counter itself is made up of U345 and U346,
which are up/down binary counters (74LS193). Since each
counter is capable of counting only four bits, two such ICs
are necessary to extend the count to the necessary eight
bits.
At the appropriate time, the counters are loaded through
their parallel inputs with data from LJ347. This IC is a serial-
in, parallel-out shift register, which stores control infor-
mation from the 80-bit serial control word. Data originating
in the microcomputer section is shifted into U347 under
the control of microcomputer software. The actual count
data will depend on the programmed number of samples.
Once the counter is loaded, it will count one unit with each
sample. Once the count is complete, an output pulse at
the BORROW terminal of U346 is generated. This pulse
ultimately controls the RUN/STOP flip-flop, U368A.
6.5.5 Digital Trigger Comparator Circuits
The digital comparator circuits are located on drawing
number 194-126, pages 2 and 3.
ICs associated with the digital comparator circuits include
U356, U357, and U358 (page 3), and U348, LJ349, U350,
U327A, U353, and U354 (page 2). U349, U350, U357, and
U358 are 4.bit magnitude comparator ICs (74LS85). These
ICs compare the difference between the A/D binary data
stored in U351 and U359, and binary trigger level infor-
mation stored in U348 and U356. U348 and U356 are serial-
in, parallel-out shift registers (74LSl64) that store the binary
trigger level information. That trigger level information is
part of the 80.bit serial control word, and is shifted in
serially. It is derived from the programmed trigger level
keyed in by the operator, or programmed over the IEEE-488
bus.
The digital comparators work in conjunction with U353
and U354 to generate a compare pulse when the A/D data
goes through a transition point below or above that set by
trigger level data. These ICs are set up differently depen-
ding on whether positive or negative slope triggering is
in effect. For example, if negative slope trigger is pro-
grammed, the compare pulse will be generated when the
AID data goes below the preset trigger level stored in U348
and U356. When the compare pulse is generated, the A/D
reading sequence is started and will run in accordance with
the programmed rate and number of samples.
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