Keithley 194 Instruction Manual page 164

PRINCIPLES OF OPERATION
The digital comparator circuits operate only when the
selected trigger source in the input signal. Thus, these cir-
cuit have no effect on AID converter sampling for other
trigger sources.
6.5.6 Trigger Period Control Logic
The trigger period control logic may be found on drawing
number 194-126, page 3. The purpose of this circuitry is
to generate A/D converter trigger pulses at programmed
intervals.
This control logic is made up of two l2-bit latches (U306
and half of U310), a l2-bit counter (U307, U308, and U309),
and miscellaneous gates and flip-flops. U306 and U310 are
serial-in, parallel-out shift registers (74LS164), while U307.
U308, and U309 are synchronous presettable binary
counters (74LS161).
Counter control data is first loaded serially into U306 and
U310 from the SO-bit serial control word. This binary in-
formation will depend on the programmed sampling rate.
Once all bits are in the 74LS164 shift registers, they are
strobed into the counter ICs to begin the counting process.
This loading operation is carried out by setting the LOAD
terminals of U307, U308, and U309 low.
The trigger period counters are controlled by a clock pulse
applied to the CLK inputs of the three ICs. Normally, the
1OMHz MPU clock is used, but an external clock signal will
be used instead if a suitable clocking signal is applied to
the EXT CLOCK INPUT on the rear panel of the
instrument.
During the count-up process, the MPU monitors the state
of the 0, terminal of U309. When it goes high, a software
counter is incremented, the counter is then reloaded with
data from U306 and U310, and the process repeats. Once
both the hardware and software counters have reached the
required count values, the process is terminated, as the
programmed number of samples have been taken.
6.5.7 64K Byte Dual-Port Memory
Elements of the 64K byte dual-port memory include the
memory ICs, the dynamic memory controller, the address
bus multiplexer, an address counter, and the data bus
multiplexer. These components can be found on drawing
number 194.126, pages 3 and 4, located at the end of Sec-
tion 8.
Memory Storage and Control
The memory KS are U317-U320 and U337-U340. Each of
these devices is a 64K X 1 bit dynamic RAM (6665A). Each
IC stores one bit of the 64K bytes of available storage. An
individual storage element within the IC is actually a vcr>
small capacitor. Since the stored charge periodically leaks
off, the dynamic RAMS must be periodically refreshed.
Dynamic RAM refreshing is one task performed by the
dynamic memory controller IC, U316 (4500). Refresh is ac-
complished by placing the RAS line low approximateI!
every @sec. Since 128 rows are present in each IC, each
row is refreshed approximately every lmsec. The dynamic
memory controller alsa multiplexes addresses fur the
memory KS since those devices have only eight address
lines.
Each memory IC is organized into a 128 bit X 512 bit ro\v-
column matrix. Thus, to address a specific memory cle-
ment or bit, both a row address and a column address
must be provided. This sequence is autom.~tically per-
formed by U316. The TOW or column address is placed on
the MAO-MA7 lines, and the appropriate strobe line, CAS
(column address strobe) or RAS (row address strobe) is
then set low. Once the addresses are strobed int<j th<,
memory ICs, the data bits can be accessed through the 11
and Q lines. In order to write to the memory ICs, the It
line must be placed low.
Address Counter and Multiplexers
U3l2 and U334 maintain the address count for the A L1
converter. Each of these ICs is dual &bit bin+ ripple
counter (74LS393). As wch AiD data byte is stored. the
counter is incremented so that the subsequent data byte
is stored in the next higher memory location.
As pointed out earlier, the AiD converter and the
microprocessor share the dual-port memory- In urdcr, to
do so, the address and data lines are multlplexcd, wth
the A/D converter circuits or the MPU gaining access to
the memory ICs at the appropriate times. U313, U314.
U335, and U336 perform the multiplexing function for the
address lines. Each of these ICs is an octal buffer with
3-state outputs (74LS244). The multiplexing action is per-
formed by turning on the outputs of the appropriate pair
of ICs to address the desired memory location. When AID
data is being stored, the outputs of LJ313 and U335 will
be on and the outputs of U314 and U336 will be off. Con-
versely, the outputs of U314 and U336 will be on and the
U313 and U335 outputs will be off when the
microprocessor is accessing the memory circuits.
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