IDEC FC6A-C16K1CE Communications Manual page 33

■ D8104: Control Signal Status (Port 1 to 3)
The signal statuses of the DSR and DTR controls lines are written to this register. This register is updated in END processing
when stopped and while running. The allocation of communication ports in the device (bit assignment) is as follows.
Bit
15
0 (00): DTR and DSR are both off.
1 (01): DTR is off and DSR is on.
2 (10): DTR is on and DSR is off.
3 (11): DTR and DSR are both on.
■ D8105: RS232C DSR Input Control Signal Option (Port 1 to 3)
The signal statuses of the DSR and DTR controls lines are written to this register. This register is updated in END processing
when stopped and while running. The allocation of communication ports in the device (bit assignment) is as follows.
Bit
15
0 (000): The DSR signal status is not used for FC6A Series MicroSmart transmission control.
Use this status when DSR signal control is not required.
1 (001): When the DSR signal is on, the FC6A Series MicroSmart can transmit and receive.
DSR signal
OFF
Transmit/receive
2 (010): When the DSR signal is off, the FC6A Series MicroSmart can transmit and receive.
DSR signal
OFF
Transmit/receive
3 (011): When the DSR signal is on, transmission is possible (reception is always possible).
DSR signal
OFF
Transmit
This is normally called "busy control" and is used for transmission control for devices with a slow
processing speed such as printers.
(As viewed from the connected device, there is a limit on the data that can be input.)
4 (100): When the DSR signal is off, transmission is possible.
DSR signal
OFF
Transmit
5 or higher: The operation is the same as the setting "000".
FC6A S
Bit Bit
8 7 5 4 3
Bit Bit
8 7 6 5 4
ON
Not possible Possible
ON
Not possible Possible
ON
Not possible Possible
ON
Not possible Possible
M S A
ERIES ICRO MART LL
Bit
2 1 0
Port 1
Port 2
Port 3
Bit Bit
3 2 1 0
Port 1
Port 2
Port 3
Not possible
Not possible
Not possible
Not possible
- -O T C
IN NE YPE OMMUNICATION
M FC9Y-B1730
ANUAL
2: D
EVICE
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