Lattice Semiconductor MachXO2 User Manual page 7

Table 2-1. LPDDR SDRAM Memory Controller Top-Level I/O List for Generic Interface (Continued)
Port Name
data_mask[(DSIZE/8)-1:0]
sclk
init_done
cmd_rdy
data_rdy
read_data[DSIZE-1:0]
read_data_valid[1:0]
Table 2-2 describes the user interface signals at the top level I/O for Wishbone Interface.
Table 2-2. LPDDR SDRAM Memory Controller Top-Level I/O List for Wishbone Interface
Port Name
PORT0_ARRD_I[31:0],
PORT1_ARRD_I[31:0]
PORT0_DAT_I[31:0],
PORT1_DAT_I[31:0]
PORT0_SEL_I[4:0],
PORT1_SEL_I[4:0]
PORT0_WE_I,
PORT1_WE_I
PORT0_CYC_I[2:0],
PORT1_CYC_I[2:0]
PORT0_CLK_I,
PORT1_CLK_I
RST_I
IPUG92_01.2, October 2012
Active State I/O
N/A Input
N/A Output
High Output
High Output
High Output
N/A Output
High Output
I/O
The address input array used to pass a binary address.
For LPDDR memory of:
1G :
PORT0_ARRD_I[25:0] = valid address
PORT0_ARRD_I[31:26] = unused
512M :
PORT0_ARRD_I[24:0] = valid address
PORT0_ARRD_I[31:25] = unused
Input
256M :
PORT0_ARRD_I[23:0] = valid address
PORT0_ARRD_I[31:24] = unused
128M :
PORT0_ARRD_I[22:0] = valid address
PORT0_ARRD_I[31:23] = unused
64M :
PORT0_ARRD_I[21:0] = valid address
PORT0_ARRD_I[31:22] = unused
Input The data input array used for write data
The select input array indicates where valid data is placed on the DAT_I( ) signal array
Input during WRITE cycles and where it should be present on the DAT_O( ) signal array
during READ cycles.
The write enable Input WE_I indicates whether the current local bus cycle is a
Input READ or WRITE cycle. The signal is negated during READ cycles and is
asserted during WRITE cycles
The Cycle Input CYC_I, when asserted, indicates that a valid bus cycle is in progress.
The signal is asserted for the duration of all bus cycles.
Input
The CYC_I signal is asserted during the first data transfer and remains asserted until
the last data transfer.
Input Wishbone input clocks
Input Wishbone reset
Data mask input for write_data.
System clock output. The user logic uses this as a system
clock unless an external clock generator is used.
Initialization done output. It is asserted for one clock cycle
when the core completes the memory initialization routine.
Command ready output. When asserted, it indicates the core
is ready to accept the next command and address.
Data ready output. When asserted, it indicates the core is
ready to receive the write data.
Read data output from the memory to the user logic.
Read data valid output. When asserted, it indicates the data
on the read_data bus is valid. The two bits are independent
outputs of the two DQSBUFH used in the design.
If the LPDDR IO training and alignment is achieved, the bits
of the read_data_valid bus should be identical.
Description
7 LPDDR SDRAM Controller User's Guide
Functional Description
Description