I/O Training Block; Data Control Block; Lpddr I/Os; Command Application Logic Block - Lattice Semiconductor MachXO2 User Manual

This module is automatically activated at the exit of a deep power down operation and the LPDDR memory is re-ini-
tialized.

I/O Training Block

The I/O Training Block adjusts the MachXO2 I/Os for write/read operations. It is automatically activated at the end
of an initialization sequence and at the end of every auto refresh burst. It is an IPexpress GUI-programmable
parameter. The user may choose to perform training each time the memory is initialized or periodically at the end of
every auto refresh burst. The memory reserved space for training patterns is for addresses 14'h0 - 14'hF of row 0
of bank 0.

Data Control Block

The Data Control Block interfaces with the LPDDR I/O modules and is responsible for generating the control sig-
nals for the I/Os for write/read operations. This block implements all the logic needed to ensure that the data
write/read to and from the memory is transferred to the local user interface in a deterministic and coherent manner.

LPDDR I/Os

The LPDDR I/O modules are MachXO2 device primitives that directly connect to the LPDDR memory. These prim-
itives implement all the interface signals required for memory access. They convert the single data rate (SDR) data
to double rate LPDDR data for write operations and perform the LPDDR to SDR conversion in read mode.

Command Application Logic Block

The Command Application Logic (CAL) Block accepts and processes the decoded internal command sequences
from the Command Decode Logic. It translates each sequence into memory commands that meet the JEDEC pro-
tocol sequences and timing requirements of the LPDDR memory device. It is the module responsible for protocol
compliance.

Command Decode Logic Block

The Command Decode Logic (CDL) Block accepts user commands from the local interface and decodes them to
generate a sequence of internal memory commands depending on the current command and the status of current
bank and row. It tracks the open/close status of every bank and stores the row address of every opened bank. The
controller implements a command pipeline to improve throughput. With this capability, the next command in the
queue is decoded while the current command is presented at the memory interface.

Signal Descriptions

Table 2-1 describes the user interface signals at the top level.
Table 2-1. LPDDR SDRAM Memory Controller Top-Level I/O List for Generic Interface
Port Name
Local User Interface
clk_in
rst_n
init_start
cmd[3:0]
cmd_valid
addr[ADDR_WIDTH-1:0]
write_data[DSIZE-1:0]
IPUG92_01.2, October 2012
Active State I/O
N/A In
Low Input
High Input
N/A Input
High Input
N/A Input
N/A Input
Reference clock. It is connected to the PLL input.
Asynchronous reset. It resets the entire IP core when
asserted.
Initialization start request. Should be asserted to initiate
memory initialization either right after the power-on reset or
before sending the first user command to the memory con-
troller
User command input to the memory controller.
Command and address valid input. When asserted, the addr
and cmd inputs are valid.
User read or write address input to the memory controller.
Write data input from user logic to the memory controller. The
user side write data width is two times the memory data bus
6 LPDDR SDRAM Controller User's Guide
Functional Description
Description