Evaluation Script File; Instantiating The Core; Running Functional Simulation; Synthesizing And Implementing The Core In A Top-Level Design - Lattice Semiconductor MachXO2 User Manual

Evaluation Script File

ModelSim and Aldec Active-HDL simulation macro script files are included for instant evaluation of the IP core. All
required files for simulation are included in the macro script. This simulation script can be used as a starting point
of a user simulation project.

Instantiating the Core

The generated LPDDR SDRAM IP core package includes black-box (<username>_bb.v) and instance (<user-
name>_inst.v) templates that can be used to instantiate the core in a top-level design. An example RTL top-level
reference source file that can be used as an instantiation template for the IP core is provided in 
\<project_dir>\lpddr_eval\<username>\src\top. Users may also use this top-level reference as the
starting template for the top-level for their complete design.

Running Functional Simulation

Simulation support for the LPDDR SDRAM IP core is provided for Aldec and ModelSim simulators. The LPDDR
SDRAM core simulation model is generated from the IPexpress tool with the name <username>.v. This file calls 
<username>_beh.v which contains the obfuscated simulation model. An obfuscated simulation model is Lattice's
unique IP protection technique which scrambles the Verilog HDL while maintaining logical equivalence. VHDL
users will use the same Verilog model for simulation.
When compiling the LPDDR SDRAM IP core the following files must be compiled with the model.
• pci_exp_params.v
• pci_exp_ddefines.v
These files provide "define constants" that are necessary for the simulation model.
The ModelSim environment is located in \<project_dir>\lpddr_eval\<username>\sim\modelsim. Users
can run the ModelSim simulation by performing the following steps:
1. Open ModelSim.
2. Under the File tab, select Change Directory and choose folder
\<project_dir>\lpddr_eval\<username>\sim\modelsim.
3. Under the Tools tab, select Tcl > Execute Macro and execute one of the ModelSim "do" scripts shown, depend-
ing on which version of ModelSim is used (ModelSim SE or the Lattice OEM version).
The Aldec Active-HDL environment is located in \<project_dir>\lpddr_eval\<username>\sim\aldec.
Users can run the Aldec evaluation simulation by performing the following steps:
1. Open Active-HDL.
2. Under the Tools tab, select Execute Macro.
3. Browse to the directory \<project_dir>\lpddr_eval\<username>\sim\aldec and execute the Active-
HDL "do" script shown.

Synthesizing and Implementing the Core in a Top-Level Design

The LPDDR SDRAM IP core itself is synthesized and provided in NGO format when the core is generated through
the IPexpress tool. You can combine the core in your own top-level design by instantiating the core in your top level
file as described in "Instantiating the Core" on page 25
Synthesis.
The top-level file <username>_eval_top.v provided in 
\<project_dir>\lpddr_eval\<username>\src\top
IPUG92_01.2, October 2012
and then synthesizing the entire design with Synplify RTL
25 LPDDR SDRAM Controller User's Guide
IP Core Generation