Lattice Semiconductor MachXO2 User Manual page 3

Getting Started .................................................................................................................................................... 20
Chapter 4. IP Core Generation............................................................................................................. 20
IPexpress-Created Files and Top Level Directory Structure............................................................................... 22
LPDDR SDRAM Controller IP Core File Structure.............................................................................................. 22
Top-level Wrapper...................................................................................................................................... 23
Obfuscated Module for the Core ................................................................................................................ 23
Obfuscated Module for the I/O Modules .................................................................................................... 23
Simulation Files for IP Core Evaluation............................................................................................................... 24
Test Bench Top.......................................................................................................................................... 24
Obfuscated Core and I/O Simulation Models............................................................................................. 24
Command Generator ................................................................................................................................. 24
Monitor ....................................................................................................................................................... 24
Memory Model ........................................................................................................................................... 24
Memory Model Parameter.......................................................................................................................... 24
Evaluation Script File ................................................................................................................................. 25
Instantiating the Core .......................................................................................................................................... 25
Running Functional Simulation ........................................................................................................................... 25
Synthesizing and Implementing the Core in a Top-Level Design ....................................................................... 25
Hardware Evaluation........................................................................................................................................... 26
Enabling Hardware Evaluation................................................................................................................... 26
Updating/Regenerating the IP Core .................................................................................................................... 26
Regenerating an IP Core ........................................................................................................................... 26
Chapter 5. Application Support........................................................................................................... 28
Core Implementation........................................................................................................................................... 28
Understanding Preferences ................................................................................................................................ 28
Chapter 6. Core Verification ................................................................................................................ 29
Chapter 7. Support Resources ............................................................................................................ 30
Lattice Technical Support.................................................................................................................................... 30
Online Forums............................................................................................................................................ 30
Telephone Support Hotline ........................................................................................................................ 30
E-mail Support ........................................................................................................................................... 30
Local Support ............................................................................................................................................. 30
Internet ....................................................................................................................................................... 30
References.......................................................................................................................................................... 30
JEDEC Web Site................................................................................................................................................. 30
Revision History .................................................................................................................................................. 31
Appendix A. Resource Utilization ....................................................................................................... 32
MachXO2 Devices .............................................................................................................................................. 32
Ordering Part Number......................................................................................................................................... 32
IPUG92_01.2, October 2012 3 LPDDR SDRAM Controller User's Guide
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