Power Down And Deep Power Down; User Commands For Wishbone Interface - Lattice Semiconductor MachXO2 User Manual

Figure 2-5. User-Side Read Operation
read_data_valid
read_data_valid
READA
READA is treated in the same way as a READ command except that the core issues a Read with Auto Precharge
command to the memory instead of a READ command. This makes the memory automatically close the current
row after completing the read operation.
AUTO REFRESH
Since LPDDR memories have at least an 8-deep Auto Refresh command queue as per the JEDEC specification,
the Lattices LPDDR memory controller core can support up to eight Auto Refresh commands in one burst. The
core has an internal Auto Refresh Generator that sends out a set of consecutive Auto Refresh commands to the
memory at once when it reaches the time period of the refresh intervals (t
selected in the IPexpress GUI. It is recommended that the maximum number be used if the LPDDR interface
throughput is a major concern of the system. If it is set to eight, for example, the core will send a set of eight con-
secutive Auto Refresh commands to the memory once it reaches the time period of the eight refresh intervals (t
x 8). Bursting refresh cycles increases the LPDDR bus throughput because it helps keep core intervention to a
minimum. Upon completion of an Auto Refresh burst, the controller will automatically retrain the I/Os if the periodic
retraining of the I/Os is selected from the IPexpress GUI.
SELF REFRESH
The self refresh command comes as a set of two in compliance to JEDEC protocol: self refresh entry and self
refresh exit. The user should always use them as a set, a self refresh exit should always follow a self refresh entry.
To minimize power, the user has the option to turn the memory clock off during self refresh operations. This is a
user-programmable parameter, and when set, the controller will automatically turn off the memory clock. To mini-
mize the power even further, the controller will refresh half or a quarter of the memory if it is set through an MRS
command.

Power Down and Deep Power Down

The power down commands come as a set of two in compliance to JEDEC protocol: entry and exit. The user
should always use them as a set an exit should always follow an entry. To minimize power, the user has the option
to turn the memory clock off during power-down operations. For deep power entry, the controller will re-initialize the
memory upon exiting the deep power down state, and retrain the I/Os if it is selected from the GUI.

User Commands for Wishbone Interface

The LPDDR controller has a GUI selectable interface compliant to two port WISHBONE bus. Port_0 is used for
read/writes and port_1 for programming the memory.
IPUG92_01.2, October 2012
Burst length = 2
read_data
D0
read_data
Burst length = 4
D0 D1
Burst length = 8
D0 D1
) times the Auto Refresh burst count
REFI
11 LPDDR SDRAM Controller User's Guide
Functional Description
D1 D1
REFI