Chapter 2. Functional Description; Overview; Initialization Block - Lattice Semiconductor MachXO2 User Manual

Overview

The LPDDR memory controller consists of two major parts: the controller core logic module and the I/O logic mod-
ule. This section briefly describes the operation of each of these modules.
diagram illustrating the main functional blocks and the technology used to implement the LPDDR SDRAM Control-
ler IP core functions.
Figure 2-1. LPDDR SDRAM Controller Block Diagram
clk_in
rst_n
cmd
cmd_valid
addr
init_start
ar_burst_cnt
init_done
cmd_rdy
datain
dmsel
data_rdy
read_data
read_data_valid
The core module has several functional sub-modules: Initialization Block, Command Decode Logic Block, Com-
mand Application Logic Block, Data Control Block and I/O Training Block. LPDDR I/O modules provide the PHY
interface to the memory device. This block mostly consists of MachXO2 device I/O primitives supporting compli-
ance to LPDDR electrical and timing requirements.

Initialization Block

The Initialization Block performs the LPDDR memory initialization sequence as defined by the JEDEC protocol.
After power-on or a normal reset of the LPDDR controller, memory must be initialized before sending any com-
mand to the Controller. It is the user's responsibility to assert the init_start input to the LPDDR controller to start the
memory initialization sequence. The completion of initialization is indicated by the init_done output provided by this
block.
IPUG92_01.2, October 2012
Configuration Interface
t t t
RC RP XP
Initialization
Command
Decode
Logic
I/O Training
Functional Description
Figure 2-1
t t
RCD SRR
Command
Application
Logic
Data Control
5 LPDDR SDRAM Controller User's Guide
Chapter 2:
provides a high-level block
em_ddr_cs_n
em_ddr_ras_n
em_ddr_we_n
em_ddr_cas_n
em_ddr_cke
em_ddr_clk
em_ddr_addr
em_ddr_ba
em_ddr_dm
I/Os
em_ddr_data
em_ddr_dqs