Chapter 5. Application Support; Core Implementation; Understanding Preferences - Lattice Semiconductor MachXO2 User Manual

Lpddr sdram controller ip core

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This chapter provides application support information for the MachXO2 LPDDR SDRAM Controller IP core.

This section describes the major factors that are important for a successful LPDDR memory controller implementa-

tion.

The following preferences are found in the provided logical preference files (.lpf):

• FREQUENCY – The LPDDR SDRAM Controller IP core is normally over-constrained for obtaining optimal f

results. The post-route trace preference file contains the preferences that have the real performance targets, and

it should be used to validate the timing results.

• IOBUF – The IOBUF preference assigns the required I/O types to the LPDDR I/O pads.

• LOCATE – For all MachXO2 devices the memory data and data strobe pins are located at the right side of the

device. For this reason these I/Os are grouped and locked to Bank 1.

IPUG92_01.2, October 2012

Application Support

LPDDR SDRAM Controller User's Guide

Chapter 5:

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