1. Manuals
  2. Brands
  3. Lattice Semiconductor Manuals
  4. Controller
  5. 10 Gb+ Ethernet MAC IP
  6. User manual

Lattice Semiconductor 10 Gb+ Ethernet MAC IP User Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
10 Gb+ Ethernet MAC IP Core User's Guide
December 2010
IPUG39_02.9

Advertisement

Table of Contents
loading

Related Manuals for Lattice Semiconductor 10 Gb+ Ethernet MAC IP

Summary of Contents for Lattice Semiconductor 10 Gb+ Ethernet MAC IP

  • Page 1 10 Gb+ Ethernet MAC IP Core User’s Guide December 2010 IPUG39_02.9...

  • Page 2: Table Of Contents

    LatticeSC/M FPGAs ............................48 © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
  • Page 3 Lattice Semiconductor Table of Contents Ordering Part Number..........................48 IPUG39_02.9, December 2010 10 Gb+ Ethernet MAC IP Core User’s Guide...

  • Page 4: Chapter 1. Introduction

    Introduction This document provides technical information about the Lattice 10 Gigabit Plus (10 Gb+) Ethernet Media Access Controller (MAC) Intellectual Property (IP) core. The 10 Gb+ Ethernet MAC IP core comes with the following docu- mentation and files: • Protected netlist/database •...
  • Page 5 Data rates up to 12Gbps are supported by increasing the 10 Gb+ Ethernet MAC system clock rate from the stan- dard frequency of 156.25MHz used for processing 10Gbps data up to frequencies as high as 187.50MHz. IPUG39_02.9, December 2010 10 Gb+ Ethernet MAC IP Core User’s Guide...

  • Page 6: Chapter 2. Functional Description

    Chapter 2: Functional Description This chapter provides a functional description of the 10 Gb+ Ethernet MAC IP core. Figure 2-1 shows a top-level interface diagram for the 10 Gb+ Ethernet MAC IP. Figure 2-1. 10 Gb+ Ethernet MAC Core Block Diagram...
  • Page 7 Lattice Semiconductor Functional Description Figure 2-2 shows a system block diagram for the 10 Gb+ Ethernet MAC IP core. Figure 2-2. 10 Gb+ Ethernet MAC Core System Block Diagram XGMII xgmii_tx_clk ODDR xgmii_rx_clk txmac_clk_ref reset_n IODDR tx_paustim[15:0] txmac_clk xgmii_txd[31:0] tx_pausreq...

  • Page 8: Receive Mac

    • Determines the type of the frame by analyzing the Length/Type field. • Checks for any errors in the frame by recalculating the CRC and comparing it with the expected value. IPUG39_02.9, December 2010 10 Gb+ Ethernet MAC IP Core User’s Guide...
  • Page 9 Since the internal data path is 64 bits wide, the latency from the time a frame appears at the XGMII input to the time it begins to transfer to the FIFO will be eight clock cycles. IPUG39_02.9, December 2010 10 Gb+ Ethernet MAC IP Core User’s Guide...

  • Page 10: Transmit Mac

    I/O ports on the core. Registers must be added to the top level to control and mon- itor these ports. A reference description of a set of registers to do this is included as an appendix to this user's guide. IPUG39_02.9, December 2010 10 Gb+ Ethernet MAC IP Core User’s Guide...

  • Page 11: Signal Descriptions

    Lattice Semiconductor Functional Description Signal Descriptions Table 2-3. 10 Gb+ Ethernet MAC IP Core Input and Output Signals Port Name Active State I/O Type Description reset_n Input Asynchronous reset signal – Resets the entire core when asserted. Contains parameters to be transmitted in a pause frame. Valid when...
  • Page 12 Lattice Semiconductor Functional Description Table 2-3. 10 Gb+ Ethernet MAC IP Core Input and Output Signals (Continued) Port Name Active State I/O Type Description rx_eof High Output End of frame signal asserted with the last segment of the frame. When asserted, indicates that the frame had a length error, a termination...

  • Page 13: Timing Specifications

    Lattice Semiconductor Functional Description Table 2-3. 10 Gb+ Ethernet MAC IP Core Input and Output Signals (Continued) Port Name Active State I/O Type Description vlan_tag[15:0] Output The most recently received VLAN tag. When asserted, indicates that the contents of the vlan_tag bus are valid.

  • Page 14: Chapter 3. Parameter Settings

    16for a description on how to generate the IP. Table 3-1 provides the list of user configurable parameters for the 10 Gb+ Ethernet MAC IP core. The parameter settings are specified using the 10 Gb+ Ethernet MAC IP core Configuration GUI in IPexpress.

  • Page 15: Evaluation Generation Options

    Management Statistics This parameter determines whether the optional Statistics Counters will be included in the reference design. Bits in Counters[13-40] This parameter determines the width of the optional Statistics Counters. IPUG39_02.9, December 2010 10 Gb+ Ethernet MAC IP Core User’s Guide...

  • Page 16: Chapter 4. Ip Core Generation

    Chapter 4: IP Core Generation This chapter provides information on how to generate the 10 Gb+ Ethernet MAC IP core using the Diamond or isp- LEVER software IPexpress tool, and how to include the core in a top-level design. Licensing the IP Core An IP core- and device-specific license is required to enable full, unrestricted use of the 10 Gb+ Ethernet MAC IP core in a complete, top-level design.
  • Page 17 To create a custom configuration, the user clicks the Customize button in the IPexpress tool dialog box to display the 10 Gb+ Ethernet MAC IP core Configuration GUI, as shown in Figure 4-2. From this dialog box, the user can select the IP parameter options specific to their application.

  • Page 18: Ipexpress-Created Files And Top Level Directory Structure

    When the user clicks the Generate button in the IP Configuration dialog box, the IP core and supporting files are generated in the specified “Project Path” directory. The directory structure of the generated files is shown in Figure 4-3. IPUG39_02.9, December 2010 10 Gb+ Ethernet MAC IP Core User’s Guide...
  • Page 19 Lattice Semiconductor IP Core Generation Figure 4-3. LatticeECP3 10 Gb+ Ethernet MAC IP Core Directory Structure Table 4-1 provides a list of key files and directories created by the IPexpress tool and how they are used. The IPex- press tool creates several files that are used throughout the design cycle. The names of most of the created files are customized to the user’s module name specified in the IPexpress tool.

  • Page 20: Instantiating The Core

    <username>_eval/<username>_/src/rtl/top/ directory. These are all of the files necessary to implement and verify the 10 Gb+ Ethernet MAC IP core in your own top-level design. The following additional files providing IP core generation status information are also generated in the “Project Path”...

  • Page 21: Synthesizing And Implementing The Core In A Top-Level Design

    Synthesizing and Implementing the Core in a Top-Level Design The 10 Gb+ Ethernet MAC IP core itself is synthesized and is provided in NGO format when the core is generated. Users may synthesize the core in their own top-level design by instantiating the core in their top level as described previously and then synthesizing the entire design with either Synplify or Precision RTL Synthesis.
  • Page 22 3. Select and open <username>.syn. At this point, all of the files needed to support top-level synthesis and imple- mentation will be imported to the project. 4. Select the device top-level entry in the left-hand GUI window. IPUG39_02.9, December 2010 10 Gb+ Ethernet MAC IP Core User’s Guide...

  • Page 23: Hardware Evaluation

    Hardware Evaluation The 10 Gb+ Ethernet MAC IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to create versions of the IP core that operate in hardware for a limited period of time (approximately four hours) with- out requiring the purchase of an IP license.

  • Page 24: Regenerating An Ip Core In Isplever

    As the options change, the schematic diagram of the IP core changes to show the I/O and the device resources the IP core will need. 7. Click Generate. 8. Click the Generate Log tab to check for warnings and error messages. IPUG39_02.9, December 2010 10 Gb+ Ethernet MAC IP Core User’s Guide...

  • Page 25: Chapter 5. Application Support

    Chapter 5: Application Support This chapter gives application support information for the 10 Gb+ Ethernet MAC IP core. Reference Register Descriptions There are no registers in this IP core. All control and status information is passed between the core and the top level of the device through individual I/O ports on the core.
  • Page 26 Lattice Semiconductor Application Support Table 5-1. 10 Gb+ Ethernet MAC IP Core Internal Registers (Continued) Internal Registers Register Description Mnemonic I/O Address Reset Value FIFO Almost Full Register FIFOAFT_0 B04H FIFO Almost Full Register FIFOAFT_1 B05H FIFO Almost Empty Register...
  • Page 27 Lattice Semiconductor Application Support Table 5-1. 10 Gb+ Ethernet MAC IP Core Internal Registers (Continued) Internal Registers Register Description Mnemonic I/O Address Reset Value Receive Packet Jabbers Statistics Counter RX_PKT_JABBERS 968H Receive Packet 64 Statistics Counter RX_PKT_64 970H Receive Packet 65-127 Statistics Counter...
  • Page 28 FCS and any padding bytes before transferring it to the FIFO. Promiscuous Mode. When asserted, all filtering schemes are prms abandoned and the Rx MAC receives frames with any address. IPUG39_02.9, December 2010 10 Gb+ Ethernet MAC IP Core User’s Guide...
  • Page 29 Table 5-8. MAC Address Register Description Name: MAC_ADDR Address: A07H, A08H, A09H, A0AH, A0BH, A0CH Bits Name Type Default Description MAC Address. Ethernet address assigned to the port supported Mac_Addr[0-5] by the MAC. IPUG39_02.9, December 2010 10 Gb+ Ethernet MAC IP Core User’s Guide...
  • Page 30 Table 5-11. Multicast Table Register Description Name: MLT_TAB_[0-7] Address: A10H, A11H, A12H, A13H, A14H, A15H, A16H, A17H Bits Name Type Default Description Multicast Table Multicast Table. Eight tables that make a 64-bit hash. [0-7] IPUG39_02.9, December 2010 10 Gb+ Ethernet MAC IP Core User’s Guide...
  • Page 31 Table 5-15. PAUSE Opcode Register Description Name: PAUSTMR Address: B02H, B03H Bits Name Type Default Description These bits control the tx_paustim[15:0] pins on the 10G+ MAC 15:0 Pause_Time 04FFH core. IPUG39_02.9, December 2010 10 Gb+ Ethernet MAC IP Core User’s Guide...
  • Page 32 Name: RX_STAT_UNDER_RUN Address: 810H - 817H Bits Name Type Default Description Counts the total number of underrun packets transmitted. 63:0 Underrun — tx_statvec[21] is used to implement this counter. IPUG39_02.9, December 2010 10 Gb+ Ethernet MAC IP Core User’s Guide...
  • Page 33 Name: TX_STAT_BRDCST Address: 838H - 83FH Bits Name Type Default Description Counts the total number of broadcast packets transmitted. 63:0 Broadcast Packet — tx_statvec[19] is used to implement this counter. IPUG39_02.9, December 2010 10 Gb+ Ethernet MAC IP Core User’s Guide...
  • Page 34 Address: 860H - 867H Bits Name Type Default Description Counts the total number of packets transmitted without any errors. 63:0 Packet OK — tx_statvec[14] is used to implement this counter. IPUG39_02.9, December 2010 10 Gb+ Ethernet MAC IP Core User’s Guide...
  • Page 35 Bits Name Type Default Description Counts the total number of packets transmitted with length 63:0 Packet 256-511 — between 256 and 511. tx_statvec[13:8] is used to implement this counter. IPUG39_02.9, December 2010 10 Gb+ Ethernet MAC IP Core User’s Guide...
  • Page 36 Address: 8a0H - 8a7H Bits Name Type Default Description Counts the total number of packets transmitted with error. 63:0 TX Frame Error — tx_statvec[14] is used to implement this counter. IPUG39_02.9, December 2010 10 Gb+ Ethernet MAC IP Core User’s Guide...
  • Page 37 Name Type Default Description Counts the total number of packets transmitted with length Packet 9217- 63:0 — between 9217 and 16383. tx_statvec[13:0] is used to implement 16383 this counter. IPUG39_02.9, December 2010 10 Gb+ Ethernet MAC IP Core User’s Guide...
  • Page 38 Address: 920H - 927H Bits Name Type Default Description Unsupported Counts the number of packets received with unsupported 63:0 — Opcode Opcode. rx_statvec[23] is used to implement this counter. IPUG39_02.9, December 2010 10 Gb+ Ethernet MAC IP Core User’s Guide...
  • Page 39 Address: 958H - 95FH Bits Name Type Default Description Counts the number of packets received longer than the 63:0 Long Packet — max_pkt_size. rx_statvec[21] is used to implement this counter. IPUG39_02.9, December 2010 10 Gb+ Ethernet MAC IP Core User’s Guide...
  • Page 40 Counts the number of packets received with less than 64 octets in length and has either a FCS error or an Alignment error. 63:0 Packet Fragments — rx_statvec[13:6] along with rx_statvec[17] are used to implement this counter. IPUG39_02.9, December 2010 10 Gb+ Ethernet MAC IP Core User’s Guide...
  • Page 41 Description Counts the number of packets received that were between 128- 63:0 Packet 128-255 — 255 octets in length (including bad packets). rx_statvec[13:7] is used to implement this counter. IPUG39_02.9, December 2010 10 Gb+ Ethernet MAC IP Core User’s Guide...
  • Page 42 Counts the number of packets received that were less than 64 63:0 Packet Undersize — octets long and were otherwise well formed. rx_statvec[13:6] is used to implement this counter. IPUG39_02.9, December 2010 10 Gb+ Ethernet MAC IP Core User’s Guide...
  • Page 43 Counts the number of packets received with length more than Packet 1518 with 63:0 — 1518 and with a good crc. rx_statvec[21] and rx_statvec[17] are Good CRC used to implement this counter. IPUG39_02.9, December 2010 10 Gb+ Ethernet MAC IP Core User’s Guide...
  • Page 44 Counts the number of packets received that were between 9217- Packet 9217- 63:0 — 16383 octets in length (including bad packets). rx_statvec[13:0] is 16383 used to implement this counter. IPUG39_02.9, December 2010 10 Gb+ Ethernet MAC IP Core User’s Guide...

  • Page 45: Chapter 6. Support Resources

    Local Support Contact your nearest Lattice Sales Office. Internet www.latticesemi.com References LatticeECP2/M • HB1003, LatticeECP2/M Family Handbook LatticeECP3 • HB1009, LatticeECP3 Family Handbook LatticeSC/M • DS1004, LatticeSC/M Family Data Sheet IPUG39_02.9, December 2010 10 Gb+ Ethernet MAC IP Core User’s Guide...

  • Page 46: Revision History

    02.4 Title changed from “Ten-Gigabit Ethernet Plus Media Access Controller (10G+MAC) IP Core User’s Guide” to “10 Gb+ Ethernet MAC IP Core User’s Guide”. Change all occurrences of "10G+MAC" to "10 Gb+ Ether- net MAC". Updated appendices for ispLEVER 7.1 software release.

  • Page 47: Appendix A. Resource Utilization

    Buffers integrated in the LatticeECP2 series FPGA. Thus the application implementing the 10 Gb+ Ethernet MAC specification will utilize I/O pins. Ordering Part Number The Ordering Part Number (OPN) for the 10 Gb+ Ethernet MAC IP core targeting LatticeECP2 devices is  ETHER-10G-P2-U4. LatticeECP2M and LatticeECP2MS FPGAs Table A-2.

  • Page 48: Latticeecp3 Fpgas

    Buffers integrated in the LatticeECP3 series FPGA. Thus the application implementing the 10 Gb+ Ethernet MAC specification will utilize I/O pins. Ordering Part Number The Ordering Part Number (OPN) for the 10 Gb+ Ethernet MAC IP core targeting LatticeECP3 devices is  ETHER-10G-E3-U4. LatticeSC/M FPGAs Table A-4.
  • Page 49 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Lattice ETHER-10G-P2-U3 ETHER-10G-SC-U3 ETHER-10G-PM-U3 ETHER-10G-E3-U3 ETHER-10G-P2-UT3 ETHER- 10G-PM-UT3 ETHER-10G-SC-UT3 ETHER-10G-E3-U4 ETHER-10G-E3-UT4 ETHER-10G-P2-U4 ETHER-10G-P2- UT4 ETHER-10G-PM-U4 ETHER-10G-PM-UT4 ETHER-10G-SC-U4 ETHER-10G-SC-UT4...

Table of Contents