Lattice Semiconductor MachXO2 User Manual page 10

WRITE
The user initiates a memory write operation by asserting cmd_valid along with the WRITE or WRITEA command
and the address. After the WRITE command is accepted, the memory controller core asserts the datain_rdy signal
when it is ready to receive the write data from the user logic to write into the memory. Since the duration from the
time a write command is accepted to the time the datain_rdy signal is asserted is not fixed, the user logic needs to
monitor the datain_rdy signal. Once datain_rdy is asserted, the core expects valid data on the write_data bus one
clock cycle after the datain_rdy signal is asserted.
write timing. The controller decodes the addr input to extract the current row and current bank addresses and
checks if the current row in the memory device is already opened. If there is no opened row in the current bank an
ACTIVE command is generated by the controller to the memory to open the current row first. Then the memory
controller issues a WRITE command to the memory. If there is already an opened row in the current bank and the
current row address is different from the opened row, a PRECHARGE command is generated by the controller to
close opened row in the bank. This is followed with an ACTIVE command to open the current row. Then the mem-
ory controller issues a WRITE command to the memory. If the current row is already open, only a WRITE com-
mand (without any ACTIVE or PRECHARGE commands) is sent to the memory.
Figure 2-4. One-Clock Write Data Delay
clk
datain_rdy
write_data
data_mask
clk
datain_rdy
write_data
data_mask
WRITEA
WRITEA is treated in the same way as a WRITE command except that the core issues a Write with Auto Precharge
command to the memory instead of just a WRITE command. This causes the memory to automatically close the
current row after completing the WRITE operation.
READ
When the READ command is accepted, the memory controller core accesses the memory to read the addressed
data and brings the data back to the local user interface. Once the read data is available on the local user interface,
the memory controller core asserts the read_data_valid signal to tell the user logic that the valid read data is on the
read_data bus. The read data timing on the local user interface is shown in
the same row status checking scheme as mentioned in the WRITE operation. Depending on the current row status
the memory controller generates ACTIVE and PRECHARGE commands as required. Refer to the description men-
tioned in the WRITE operation for more detail.
IPUG92_01.2, October 2012
Figure 2-4
BL4
D0 D1
DM0 DM1
B L 2
D0
DM0
shows an example of the local user interface data
BL8
D2 D3 D4 D5
DM2 DM3 DM4 DM5
B L 1 6
D0 D1 D2 D3 D4
DM0 DM1 DM2 DM3 DM4
Figure
10 LPDDR SDRAM Controller User's Guide
Functional Description
D5 D6 D7
DM7
DM5 DM6
2-5. The READ operation follows