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Lattice Semiconductor ispLever Core Multi-Channel DMA Controller User Manual

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isp Lever
TM
CORE
CORE
Multi-Channel DMA Controller
User's Guide
February 2006
ipug11_04.0

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Summary of Contents for Lattice Semiconductor ispLever Core Multi-Channel DMA Controller

  • Page 1 isp Lever CORE CORE Multi-Channel DMA Controller User’s Guide February 2006 ipug11_04.0...
  • Page 2 Lattice Semiconductor Multi-Channel DMA Controller User’s Guide Introduction The Multi-Channel Direct Memory Access (MCDMA) Controller is designed to improve microprocessor system per- formance by allowing external devices to transfer information directly from the system memory and vice versa. Memory-to-memory transfer capability is also supported.
  • Page 3 Lattice Semiconductor Multi-Channel DMA Controller User’s Guide • Software DMA requests...

  • Page 4: Block Diagram

    Lattice Semiconductor Multi-Channel DMA Controller User’s Guide Block Diagram Figure 1 shows the block diagram of this core. Figure 1. Block Diagram of MCDMA Core hreq cs_n eopin_n reset iorout_n iowout_n CPU Interface iorin_n memr_n iowin_n DMA State memw_n ready...
  • Page 5 Lattice Semiconductor Multi-Channel DMA Controller User’s Guide • Illegal I/O to memory transfer mode bits • Compressed timing mode FSM Operation When a software or hardware request is received and is found to be valid (having passed the polarity, mask and mode checks), the DMA FSM in SI (Idle) state transmits a request signal, hreq to the CPU and transitions to S0 and waits for the hlda signal.
  • Page 6 Lattice Semiconductor Multi-Channel DMA Controller User’s Guide Figure 2. MCDMA Finite State Machine for 8237 and Non-8237 Modes No REQ Request Dropped LAST_TRAN/ Illegal Illegal No HDLA SINGLE_TRAN Mode I/O Mode Termination (8237 only) LAST_TRAN/ SINGLE_TRAN Termination Not LAST_TRAN S1/S11...
  • Page 7 Lattice Semiconductor Multi-Channel DMA Controller User’s Guide Table 2. State Descriptions State Description Idle State - SI Upon reset, the state machine enters the idle state, SI. The CPU can program the core’s internal registers while it is in this state. The device stays in this state until an unmasked DMA request is detected;...
  • Page 8 Lattice Semiconductor Multi-Channel DMA Controller User’s Guide Table 2. State Descriptions (Continued) State Description Memory-to-Memory Read This is the third state of the memory-to-memory transfer. The state machine sam- Transfer State Three - S13 ples the ready signal and stays in this state as long as it is asserted. The machine transitions to state S14 when the ready signal is de-asserted.
  • Page 9 Lattice Semiconductor Multi-Channel DMA Controller User’s Guide Table 2. State Descriptions (Continued) State Description Memory-to-Memory Write This is the eighth and final stage of the memory-to-memory transfer. The state transfer state four - S24 machine de-asserts the memw_n signal. In the 8237 mode, Channel 1’s current word register is decremented.

  • Page 10: Priority Request Encoder

    Lattice Semiconductor Multi-Channel DMA Controller User’s Guide Table 2. State Descriptions (Continued) State Description Active DMA state four - S4 This is the last stage of the DMA transfer. The memw_n or iowout_n signal is de- asserted, depends on the operation (I/O-to-memory or memory-to-I/O). The same thing happens to the memr_n or iorout_n signal for only one of them being de- asserted.

  • Page 11: Dma Initialization

    Lattice Semiconductor Multi-Channel DMA Controller User’s Guide The functionality of the core in the non-8237 mode is very similar to that of the 8237 mode. However, the two modes have totally different sets of programmable control registers. This increases the programmability features in the non-8237 mode.

  • Page 12: Parameter Descriptions

    Lattice Semiconductor Multi-Channel DMA Controller User’s Guide • Demand Transfer Mode: In demand transfer mode, the device is programmed to continue making transfers until a Terminal Count or external eopin_n is encountered or until dreq goes inactive. Thus, transfers continue until the I/O device has exhausted its data capacity.

  • Page 13: Signal Descriptions

    Lattice Semiconductor Multi-Channel DMA Controller User’s Guide Signal Descriptions Table shows the input and output ports of the MCDMA core that apply for both 8237 and non-8237 modes. Table 4. Signal Definitions of the MCDMA Controller Port Name Type Active State...

  • Page 14: Timing Specifications

    Lattice Semiconductor Multi-Channel DMA Controller User’s Guide Table 4. Signal Definitions of the MCDMA Controller (Continued) Port Name Type Active State Description Output High Address Enable. This active high signal enables the 8-bit latch that contains the upper 8 address bits onto the system address bus.
  • Page 15 Lattice Semiconductor Multi-Channel DMA Controller User’s Guide Figure 4. Processor Read Timing Waveform Clock cs_n iorin_n dbout...
  • Page 16 Lattice Semiconductor Multi-Channel DMA Controller User’s Guide Figure 5 shows the timing waveform for two words DMA transfer. Figure 5. Two Word DMA Transfer Timing Waveform Clock dreq hreq hlda aout Valid Address Valid Address dack iorout_n/memr_n iowout_n/memw_n Note 1.

  • Page 17: Register Descriptions

    Lattice Semiconductor Multi-Channel DMA Controller User’s Guide Register Descriptions The 8237 and non-8237 modes of the MCDMA Controller have different types and number of internal registers. The 8237 mode has ten types of internal registers that are visible to the microprocessor while the non-8237 mode has seven types of internal registers that are visible to the microprocessor.
  • Page 18 Lattice Semiconductor Multi-Channel DMA Controller User’s Guide Mode Register Each channel has a 6-bit wide register. During a write operation by the microprocessor when MCDMA is in idle state, the least two significant bits (bit 0 and 1) of the data bus determine which channel mode register is being accessed.
  • Page 19 Lattice Semiconductor Multi-Channel DMA Controller User’s Guide Table 7. Mode Register - 8237 Mode Description 00 Channel 0 select 01 Channel 1 select 10 Channel 2 select 11 Channel 3 select 00 Verify transfer 01 Write transfer 10 Read transfer 11 Illegal xx If bits 6 &...
  • Page 20 Lattice Semiconductor Multi-Channel DMA Controller User’s Guide Table 11. Status Register: Access One Bit – 8237 Mode Description Channel 0 terminal count Channel 1 terminal count Channel 2 terminal count Channel 3 terminal count Channel 0 request Channel 1 request...
  • Page 21 Lattice Semiconductor Multi-Channel DMA Controller User’s Guide Command Register This register controls the operation of the core. This register is 4 bits wide in the non-8237 mode. A reset or master clear clears the register. Table 13 lists the functions of this register for the non-8237 mode.

  • Page 22: Register Address Map

    Lattice Semiconductor Multi-Channel DMA Controller User’s Guide Table 15. Channel Control Register – Non-8237 Mode Description Clear Request bit Set Request bit Channel unmasked Channel masked Auto Initialization disable Auto Initialization enable Register Address Map The 8237 and non-8237 modes of the MCDMA Controller decode and use different numbers of ain bit input sig- nals.

  • Page 23: Programming The Mcdma Controller

    DMA cycle. Reference Information • ispLEVER Software User Manual, Lattice Semiconductor Corporation • 8237A High Performance Programmable DMA Controller, Intel Corporation, September 1993. Technical Support Assistance...
  • Page 24 Lattice Semiconductor Multi-Channel DMA Controller User’s Guide ® Appendix for ORCA Series 4 FPGAs Table 18. Performance and Resource Utilization ORCA 4 sysMEM™ Mode Name of Parameter File LUTs PFUs Registers EBRs (MHz) 8237 dma_mc_o4_2_001.lpc 1258 Non-8237 dma_mc_o4_2_002.lpc 2661 1187 1.
  • Page 25 Lattice Semiconductor Multi-Channel DMA Controller User’s Guide ® Appendix for ispXPGA FPGAs Table 20. Performance and Resource Utilization Name of ispXPGA sysMEM Mode Parameter File LUT4 PFUs Registers EBRs (MHz) 8237 dma_mc_xp_2_001.lpc 1450 Non-8237 dma_mc_xp_2_002.lpc 3487 1072 1181 1. Performance and utilization characteristics are generated using LFX1200B-05F900C in Lattice ispLEVER 3.x software. The evaluation ver- sion of this IP core only works on this specific device density, package, and speed grade.

  • Page 26: Appendix For Latticeecp™ And Latticeec™ Fpgas

    Lattice Semiconductor Multi-Channel DMA Controller User’s Guide Appendix for LatticeECP™ and LatticeEC™ FPGAs Table 22. Performance and Resource Utilization Name of sysMEM Mode Parameter File SLICEs LUTs EBRs Registers (MHz) 8237 dma_mc_e2_3_001.lpc 1087 Non-8237 dma_mc_e2_3_002.lpc 1633 2249 1181 1. Performance and utilization characteristics are generated using LFEC20E-4F672C in Lattice ispLEVER 4.1 software. When using this IP core in a different density, package, or speed grade, performance may vary.

  • Page 27: Appendix For Latticexp™ Fpgas

    Lattice Semiconductor Multi-Channel DMA Controller User’s Guide Appendix for LatticeXP™ FPGAs Table 24. Performance and Resource Utilization Name of sysMEM Mode Parameter File SLICEs LUTs EBRs Registers (MHz) 8237 dma_mc_xm_3_001.lpc 1287 Non-8237 dma_mc_xm_3_002.lpc 1794 3084 1179 1. Performance and utilization characteristics are generated using LFXP10E-4F388C in Lattice ispLEVER 5.0 software. When using this IP core in a different density, package, or speed grade, performance may vary.

  • Page 28: Appendix For Latticesc™ Fpgas

    Lattice Semiconductor Multi-Channel DMA Controller User’s Guide Appendix for LatticeSC™ FPGAs Table 26. Performance and Resource Utilization sysMEM™ Mode Name of Parameter File SLICEs LUTs EBRs Registers I/Os (MHz) 1249 >100 8237 dma_mc_sc_3_001.lpc Non-8237 dma_mc_sc_3_002.lpc 1744 2864 1179 >100 1. Performance and utilization characteristics are generated using LFSC3GA25E-5F900C in Lattice ispLEVER 5.1 SP2 software. When using this IP core in a different density, package, or speed grade, performance may vary.
  • Page 29 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Lattice DMA-MC-E2-N3 DMA-MC-O4-N2 DMA-MC-XM-N3 DMA-MC-XP-N2 DMA-MC-SC-N3...

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