Appendix A. Resource Utilization; Machxo2 Devices; Ordering Part Number - Lattice Semiconductor MachXO2 User Manual

This appendix gives resource utilization information for Lattice CPLDs using the LPDDR SDRAM Controller IP
core. IPexpress is the Lattice IP configuration utility, and is included as a standard feature of the Diamond design
software. Details regarding the use of IPexpress can be found in the IPexpress and Diamond help systems. For
more information on the Diamond design software, visit the Lattice web site at: www.latticesemi.com/software.

MachXO2 Devices

Table A-1 lists performance and resource utilization data for four LPDDR SDRAM configurations.
Table A-1. Performance and Resource Utilization
IP Core
LPDDR SDRAM
Controller Configuration 1
LPDDR SDRAM
Controller Configuration 2
LPDDR SDRAM
Controller Configuration 3
LPDDR SDRAM
Controller Configuration 4
1. Performance and utilization data are generated using a LCMXO2-7000HE-6BG256C device in Lattice Diamond 1.3 design software. Per-
formance may vary when using this IP core in a different density, speed or grade within the MachXO2 family.
2. SDRAM data path width of 16 bits.

Ordering Part Number

The Ordering Part Number (OPN) for the LPDDR SDRAM Controller IP on MachXO2 devices is: 
LPDDRCT-WB-M2-U
IPUG92_01.2, October 2012
2
Parameter Settings SLICEs
814
705
Table 3-1 on page 14
parameter defaults
729
729
Resource Utilization
1
LUTs Registers
1530 911
1314 804
1409 969
1409 969
32 LPDDR SDRAM Controller User's Guide
Appendix A:
PAR Start
I/O Point f
MAX
149 1
149 1
143 1
143 1
(MHz)
136.4
136.6
142.9
142.9