Local-To-Memory Address Mapping - Lattice Semiconductor MachXO2 User Manual

The memory command mapping of the port_1 wishbone bus are described in
Table 2-5. Memory Command Mapping of the port_1 Wishbone Bus
PORT1_ADDR_I PORT1_DATA_I
32'h1
Valid data =[B6, ... B0]
32'h2 Valid data =[B7, ... B0]
32'h4
32'h8
32'h10
32'h20
32'h40
32'h80
32'h100
The memory addresses shown in
Table 2-6. Reserved Memory Address for Port 0
PORT0_ADDR_I
32'h0 – 32'h10

Local-to-Memory Address Mapping

Mapping local addresses to memory addresses is an important part of a system design when a memory controller
function is implemented. Users must know how the local address lines from the memory controller connect to those
address lines from the memory because proper local-to-memory address mapping is crucial to meet the system
requirements in applications such as a video frame buffer controller. Even for other applications, careful address
mapping is generally necessary to optimize system performance. On the memory side, the address (A) and bank
address (BA) inputs are used for addressing a memory device. Users can obtain this information from the device
data sheet. Figure 2-6 shows the local-to-memory address mapping of the Lattice LPDDR memory controller core.
Figure 2-6. Local-to-Memory Address Mapping for Memory Access
addr[ADDR_WIDTH-1:0]
IPUG92_01.2, October 2012
Command
MRS
EMRS
Don't Care PDE
Don't Care PDX
Don't Care DPDE
Don't Care DPDX
Don't Care SRE
Don't Care SRX
Don't Care SRR
Table 2-6 are reserved for the controller and should not used by the Port 0 user.
For Port0, responsible of Read/Writes, the memory addresses 32'h0000_0000 to 32'h0000_0010
are reserved and should not be used by the Port 0 user.
ADDR_WIDTH - 1
Row Address
(ROW_WIDTH)
Bits [B2,B1,B0] = Burst length
Bits [B3] = Burst type
Bits [B6,B5,B4] = CAS latency
---------------------------------
Bits [31, ... B7] = Don't Care
Bits [B2,B1,B0] = PASR
Bits [B4,B3] = TCSR
Bits [B7,B6,B5] = Drive Strength
---------------------------------
Bits [31, ... B8] = Don't Care
Power Down Entry
Power Down Exit
Deep Power Down Entry
Deep Power Down Exit
Self Refresh Entry
Self Refresh Exit
Status Register Read
Description
COL_WIDTH + 1 COL_WIDTH - 1
BA Address
12 LPDDR SDRAM Controller User's Guide
Functional Description
Table 2-5.
Description
0
Column Address
(COL_WIDTH)