Top-Level Wrapper; Obfuscated Module For The Core; Obfuscated Module For The I/O Modules - Lattice Semiconductor MachXO2 User Manual

Lpddr sdram controller ip core
Hide thumbs Also See for MachXO2:
Table of Contents

Advertisement

Table 4-1. File List (Continued)
File
<username>_top.[v,vhd]
<username>_generate.tcl
<username>_generate.log
<username>_gen.log
<username>.v
The LPDDR SDRAM Controller IP core consists of the following four major functional blocks:
• Top-level wrapper (RTL)
• Obfuscated memory controller core for simulation and encrypted netlist memory controller core for synthesis
• Obfuscated I/O module block for simulation and encrypted netlist I/O module block for synthesis
• Clock generator (RTL for simulation and Verilog flow synthesis or netlist for VHDL flow synthesis) All of these
blocks are required to implement the IP core on the target device.
those blocks.
Figure 4-4. File Structure of LPDDR SDRAM Controller IP Core
Local User Logic

Top-level Wrapper

The obfuscated core, obfuscated I/O modules, and the clock generator block are instantiated in the top-level wrap-
per. When a system design is made with the LPDDR SDRAM Controller IP Core, this wrapper must be instantiated.
The wrapper is fully parameterized by the generated parameter file.

Obfuscated Module for the Core

Obfuscated RTL files are used for simulation. The obfuscated core contains the memory controller function that
interfaces with the user logic on one side and with obfuscated I/O modules on the other side. An equivalent netlist
of the core is provided for synthesis.

Obfuscated Module for the I/O Modules

The obfuscated I/O module block provides device-dependent LPDDR I/O functions. This block consist of one I/O
module top file and several sub-modules that handle the LPDDR data (DQ), data mask (DM) and data strobe
(DQS) signals. An equivalent netlist of the I/O modules is provided for synthesis.
IPUG92_01.2, October 2012
This file provides a module which instantiates the LPDDR SDRAM core. This file can be easily
modified for the user's instance of the LPDDR SDRAM core. This file is located in the
lpddr_eval/<username>/src directory.
This file is created when GUI "Generate" button is pushed. This file may be run from command
line.
This is the IPexpress scripts log file.
This is the IPexpress IP generation log file
This file provides the LPDDR SDRAM core for simulation.
Parameter File
Top-Level Wrapper (RTL)
Core
(Obfuscated
Source File)
Description
Figure 4-4
depicts the interconnection among
I/O Modules
(Obfuscated
Source File)
23
LPDDR SDRAM Controller User's Guide
IP Core Generation
LPDDR Memory

Advertisement

Table of Contents
loading

Table of Contents