Simulation Files For Ip Core Evaluation; Test Bench Top; Obfuscated Core And I/O Simulation Models; Command Generator - Lattice Semiconductor MachXO2 User Manual

IP Core Generation

Simulation Files for IP Core Evaluation

Once a LPDDR SDRAM Controller IP core is generated, it contains a complete set of test bench files to simulate a
few example core activities for evaluation. The simulation environment for the LPDDR memory controller IP is
shown in Figure 4-5. This structure can be reused by system designers to accelerate their system validation.
Figure 4-5. Simulation Structure for LPDDR Memory Controller Core Evaluation
Parameter File
Testbench Top

Monitor

Top-level
Memory
Wrapper
Model
Obfuscated
Sim Model
Command
Generator
Parameters

Test Bench Top

The test bench top includes the core under test, memory model, stimulus generator and monitor blocks. It is
parameterized by the core parameter file.

Obfuscated Core and I/O Simulation Models

The obfuscated simulation models for the core and I/O modules are instantiated in the top-level wrapper. These
obfuscated simulation model must be included in the simulation.

Command Generator

The command generator generates stimuli for the core. The core initialization and command generation activities
are predefined in the provided test case module. It is possible to customize the test case module to see the desired
activities of the core.
Monitor
The monitor block monitors both the local user interface and LPDDR interface activities and generates a warning or
an error if any violation is detected. It also validates the core data transfer activities by comparing the read data
with the written data.

Memory Model

The LPDDR SDRAM Controller test bench uses a memory simulation model provided by one of the most popular
memory vendors. If a different memory model is required, it can be used by simply replacing the instantiation of the
model from the memory configuration modules located in the same folder.

Memory Model Parameter

This memory parameter file comes with the memory simulation model. It contains the parameters that the memory
simulation model needs. It is not necessary for users to change any of these parameters.
IPUG92_01.2, October 2012 24 LPDDR SDRAM Controller User's Guide